Asynchronous 1000BASE-X/SGMII over LVDS (Applicable for Non-Versal Devices) - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

The following figure shows the HDL example design that is provided for the Asynchronous 1000BASE-X/SGMII over UltraScale and UltraScale+ device LVDS implementation. The top level of the example design creates a specific example that can be simulated, synthesized and implemented. The 2.5G mode is not supported in this case. The core netlist in this implementation is identical to that of 1G/2.5G Ethernet PCS/PMA or SGMII Using a Device-Specific Transceiver.

Figure 1. Example Design for Asynchronous 1000BASE-X/SGMII over LVDS Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Clock_reset Clock_reset Sheet.6 BaseX_Byte TX and RX BITSLICE and BITSLICE_CONTROL BaseX_ByteTX and RX BITSLICE and BITSLICE_CONTROL Sheet.9 Shared Logic Shared Logic Sheet.10 Sheet.11 Sheet.12 Reset Sequence Reset Sequence Sheet.17 Sheet.20 Asynchronous LVDS Asynchronous LVDS Sheet.21 Ethernet IP Logic Ethernet IP Logic Sheet.24 Clocking Logic Clocking Logic Sheet.35 Sheet.36 Sheet.37 Sheet.38 Lane 1 Lane 1 Sheet.39 Lane 2 (Optional) Lane 2 (Optional) Sheet.40 Lane 3 (Optional) Lane 3 (Optional) Sheet.42 Sheet.43 Example Design Example Design Sheet.45 Sheet.46 Sheet.50 Asynchronous LVDS Asynchronous LVDS Sheet.51 Ethernet IP Logic Ethernet IP Logic Sheet.52 Asynchronous LVDS Asynchronous LVDS Sheet.53 Ethernet IP Logic Ethernet IP Logic Sheet.44 X17633-042919 X17633-042919