One instance of the core is generated with the Include Shared Logic in Core option. This instance contains all the clocking logic that can be shared. The remaining instances can be generated using the Include Shared Logic in Example Design option. Clock frequencies specified in the diagrams are for 1G mode.
The clocking logic for rxoutclk
can only be shared if it is
known that the transceiver and core pairs across pcs-pma instances are
synchronous. In this case the receive clock outputs of clocking module can be
used.
The following figure shows sharing clock resources across two instantiations
of the core for Virtex 7, Kintex 7 and Zynq 7000 device transceivers; Figure 2 shows the connections for
Artix 7 devices. Clock Sharing Across Multiple Cores with Transceivers shows example connections when connecting an
instance generated with Include Shared Logic in Core to an instance generated
using Include Shared Logic in Example Design. Additional cores can be added by
continuing to instantiate extra block level modules and sharing the gtrefclk_p
and gtrefclk_n
differential clock pairs. See the
7
Series FPGAs GTX/GTH Transceivers User Guide (UG476) or the
7
Series FPGAs GTP Transceivers User Guide (UG482) for more
information.
To provide the FPGA logic clocks for all core instances, select a
txoutclk
port from any transceiver and route this to a
single MMCM. The clkout0
(125 MHz) and clkout1
(62.5 MHz) outputs from this MMCM, placed onto global clock routing using BUFGs,
can be shared across all core instances and transceivers as shown.
Each transceiver and core pair instantiated has its own independent clock domains
synchronous to rxoutclk
. These are placed on BUFMR followed by
regional clock routing using a BUFR and cannot normally be shared across
multiple GTX/GTH transceivers.