Configuration and Status Vector Ports - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

The following table describe the ports that are used to configure and monitor the core if the MDIO interface is not used.

Table 1. Alternative to Optional Management Interface – Vector Signal Pinout
Signal Direction Description
status_vector[15:0] Output See Table 3 for bit description.
configuration_vector[4:0] Input Additional interface to program management Register 0 irrespective of the optional MDIO interface. See Table 1 for bit description.
configuration_valid Input This signal is valid only when the MDIO interface is present. The rising edge of this signal is the enable signal to overwrite the Register 0 contents that were written from the MDIO interface. For triggering a fresh update of Register 0 through configuration_vector, this signal should be deasserted and then reasserted.
an_adv_config_vector[15:0] Input Auto-Negotiation: this interface is used to program Register 4, irrespective of MDIO interface. For more information, see Auto-Negotiation. See Table 2 for bit description.
an_adv_config_val Input This signal is valid only when the MDIO interface is present. The rising edge of this signal is the enable signal to overwrite the Register 4 contents that were written from the MDIO interface. For triggering a fresh update of Register 4 through an_adv_config_vector, this signal should be deasserted and then reasserted.
an_restart_config Input This signal is valid only when AN is present. The rising edge of this signal is the enable signal to overwrite Bit 9 of Register 0. For triggering a fresh AN Start, this signal should be deasserted and then reasserted.
an_interrupt Output

When the MDIO module is selected through the Vivado IDE interface, this signal indicates an active-High interrupt for Auto-Negotiation cycle completion which needs to be cleared though MDIO. This interrupt can be enabled/disabled and cleared by writing to the appropriate PCS management register.

When the MDIO module is not selected, this signal indicates AN Complete, which is asserted as long as the Auto-Negotiation is complete and AN is not restarted and cannot be cleared.

  1. Signals are synchronous to the core internal 125 MHz reference clock; userclk2 when used with a device-specific transceiver; gtx_clk when used with TBI.