Additional signals are brought out of the core to program Register 0 independent of the
MDIO management interface. These signals are bundled into the
configuration_vector signal as defined in the following table.
Signals are also brought out of the core to program Register 4 independent of
the MDIO management interface. These signals are bundled into an_adv_config_vector as defined in Table 2. Status signals are also brought out
of the core to status_vector as defined in Table 3.
| Bits | Description |
|---|---|
| 0 | Unidirectional Enable. When set to 1, Enable Transmit irrespective of state of RX (802.3ah). When set to 0, Normal operation |
| 1 | Loopback Control. When the core with a device-specific transceiver is used, this places the core into internal loopback mode. In TBI mode bit 1 is connected to ewrap. When set to 1, this signal indicates to the external PMA module to enter loopback mode. |
| 2 | Power Down, When the Zynq 7000, Virtex 7, Kintex 7, and Artix 7device transceivers are used and set to 1, the device-specific transceiver is placed in a low-power state. A reset must be applied to clear. In TBI mode this bit is unused. |
| 3 | Isolate. When set to 1, the GMII should be electrically isolated. When set to 0, normal operation is enabled. |
| 4 | Auto-Negotiation Enable. This signal is valid only if the AN module is enabled through the IP catalog. When set to 1, the signal enables the AN feature. When set to 0, AN is disabled. |
| Bits | Description 1 |
|---|---|
| 0 |
For 1000BASE-X or 2500BASE-X-Reserved. For SGMII- Always 1 |
| 4:1 | Reserved |
| 5 |
For 1000BASE-X or 2500BASE-X- Full Duplex 1 = Full Duplex Mode is advertised 0 = Full Duplex Mode is not advertised For SGMII: Reserved |
| 6 | Reserved |
| 8:7 |
For 1000BASE-X or 2500BASE-X- Pause 0 0 = No Pause 0 1 = Symmetric Pause 1 0 = Asymmetric Pause towards link partner 1 1 = Both Symmetric Pause and Asymmetric Pause towards link partner For SGMII - Reserved |
| 9 | Reserved |
| 11:10 |
For 1000BASE-X or 2500BASE-X- Reserved For SGMII- Speed 1 1 = Reserved 1 0 = 1000 Mbps 0 1 = 100 Mbps 0 0 = 10 Mbps |
| 13:12 |
For 1000BASE-X or 2500BASE-X- Remote Fault 0 0 = No Error 0 1 = Offline 1 0 = Link Failure 1 1 = Auto-Negotiation Error For SGMII- Bit[13]: Reserved Bit[12]: Duplex Mode 1 = Full Duplex 0 = Half Duplex |
| 14 |
For 1000BASE-X or 2500BASE-X- Reserved For SGMII- Acknowledge |
| 15 |
For 1000BASE-X or 2500BASE-X- Reserved. Should be tied to 0 if the next page is disabled or not used. For SGMII- PHY Link Status 1 = Link Up 0 = Link Down |
|
|
| Bits | Description |
|---|---|
| 0 |
Link Status. This signal indicates the status of the link. When High, the link is valid: synchronization of the link has been obtained and Auto-Negotiation (if present and enabled) has successfully completed and the reset sequence of the transceiver (if present) has completed. When Low, a valid link has not been established. Either link synchronization has failed or Auto-Negotiation (if present and enabled) has failed to complete. When auto-negotiation is enabled, this signal is identical to Status register Bit 1.2: Link Status. When auto-negotiation is disabled, this signal is identical to status_vector Bit[1]. In this case, either of the bits can be used. |
| 1 |
Link Synchronization. This signal indicates the state of the synchronization state machine (IEEE802.3 figure 36-9) which is based on the reception of valid 8B/10B code groups. This signal is similar to Bit[0] (Link Status), but is not qualified with Auto-Negotiation. When High, link synchronization has been obtained and in the synchronization state machine, sync_status=OK. When Low, synchronization has failed. |
| 2 | RUDI(/C/). The core is receiving /C/ ordered sets (Auto-Negotiation Configuration sequences) as defined in IEEE 802.3-2008 clause 36.2.4.10. |
| 3 | RUDI(/I/). The core is receiving /I/ ordered sets (Idles) as defined in IEEE 802.3-2008 clause 36.2.4.12. |
| 4 | RUDI(INVALID). The core has received invalid data while receiving/C/ or /I/ ordered set as defined in IEEE 802.3-2008 clause 36.2.5.1.6. This can be caused, for example, by bit errors occurring in any clock cycle of the /C/ or /I/ ordered set. |
| 5 | RXDISPERR. The core has received a running disparity error during the 8B/10B decoding function. |
| 6 | RXNOTINTABLE. The core has received a code group which is not recognized from the 8B/10B coding tables. |
| 7 |
PHY Link Status (SGMII mode only). When operating in SGMII mode, this bit represents the link status of the external PHY device attached to the other end of the SGMII link (High indicates that the PHY has obtained a link with its link partner; Low indicates that is has not linked with its link partner). The value reflected is Link Partner Base AN Register 5 bit 15 in SGMII MAC mode and the Advertisement Ability register 4 bit 15 in PHY mode. However, this bit is only valid after successful completion of auto-negotiation across the SGMII link. If SGMII auto-negotiation is disabled, then the status of this bit should be ignored. When operating in 1000BASE-X mode, this bit remains Low and should be ignored. |
| 9:8 |
Remote Fault Encoding. This signal indicates the remote fault encoding (IEEE802.3 table 37-3). This signal is validated by bit 13 of status_vector and is only valid when Auto-Negotiation is enabled. In 1000BASE-X mode these values reflected Link Partner Base AN Register 5 bits [13:12]. This signal has no significance when the core is in SGMII mode with PHY side implementation and indicates 00. In MAC side implementation of the core the signal takes the value 10 to indicate the remote fault (Link Partner Base AN Register 5 bit 15 (Link bit) is 0). |
| 11:10 |
SPEED. This signal indicates the speed negotiated and is only valid when Auto-Negotiation is enabled. In 1000BASE-X or 2500BASE-X mode these bits are hard wired to 10 but in SGMII mode the signals encoding is as shown below. The value reflected is Link Partner Base AN Register 5 bits [11:10] in MAC mode and the Advertisement Ability register 4 bits [11:10] in PHY mode. 1 1 = Reserved 1 0 = 1000 Mbps; 2500 Mbps in 2.5G mode 0 1 = 100 Mbps; reserved in 2.5G mode 0 0 = 10 Mbps; reserved in 2.5G mode |
| 12 |
Duplex Mode. This bit indicates the Duplex mode negotiated with the link partner. Indicates bit 5 of Link Partner Base AN register 5 in 1000BASE-X or 2500BASE-X mode; otherwise bit 12 in SGMII mode. (In SGMII MAC and PHY mode it is register bit 5.12.) 1 = Full Duplex 0 = Half Duplex |
| 13 |
Remote Fault . When this bit is logic one, it indicates that a remote fault is detected and the type of remote fault is indicated by status_vector bits[9:8] . This bit reflects MDIO register bit 1.4. Note: This bit is only deasserted when
a MDIO read is made to status register (register1). This signal has
no significance in SGMII PHY mode or when MDIO is disabled.
|
| 15:14 |
Pause. These bits reflect the bits [8:7] of Register 5 (Link Partner Base AN register). These bits are valid only in 1000BASE-X or 2500BASE-X mode and have no significance in SGMII mode. 0 0 = No Pause 0 1 = Symmetric Pause 1 0 = Asymmetric Pause towards Link partner 1 1 = Both Symmetric Pause and Asymmetric Pause towards link partner |