Constraining the Core - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

Required Constraints

The 1G/2.5G Ethernet PCS/PMA or SGMII solution is provided with a core level XDC file. This provides constraints for the core that are expected to be applied in all instantiations of the core. This XDC file, named <component name>.xdc, can be found in the IP Sources tab of the Sources window in the Synthesis file group.

An example XDC is also provided with the HDL example design to provide the board level constraints. This is specific to the example design and, as such, is only expected to be used as a template for the user design. See Example Design. This XDC file, named <component name>_example_design.xdc, is found in the IP Sources tab of the Sources window in the Examples file group.

The core level XDC file inherits some constraints from the example design XDC file. In any system it is expected that you will also provide an XDC file to constrain the logic in which the 1G/2.5G Ethernet PCS/PMA or SGMII solution is instantiated.

Device, Package, and Speed Grade Selections

The core can be implemented in Versal, UltraScale+, Zynq 7000 SoC, Virtex 7, Kintex 7, Artix 7, and Spartan-7 devices. The modes supported for specific devices are described in Resource Utilization.

Clock Frequencies

The 1G/2.5G Ethernet PCS/PMA or SGMII solution has a variable number of clocks with the precise number required being dependent upon the specific parameterization. As the core targets various transceiver options, there are associated clock frequency requirements.

Table 1. Clock Frequencies
Clock Name Parametrization Frequency Requirement
gtrefclk Present if serial transceiver is used 125 MHz or user selectable value for UltraScale+/UltraScale devices.
txoutclk Present if serial transceiver is used 62.5 or 125 MHz depending on serial transceiver used for 1G data rate. For 2.5G data rates for 7 series and Zynq devices this clock frequency is 125 MHz, For UltraScale+/UltraScale devices the frequency is 312.5 MHz.
userclk Present if serial transceiver is used 62.5 MHz for 1G line rate. For 2.5G data rates this clock frequency is 156.25 MHz.
userclk2 Present if serial transceiver is used 125 MHz for 1G data rates. For 2.5G data rates this clock frequency is 312.5 MHz.
sgmii_clk Present in SGMII Mode 1.25 MHz, 12.5 MHz or 125 MHz for 1G data rates. For 2.5 data rates 312.5 MHz is applicable because the core supports only the 2.5 Gbps data rate.
rxoutclk Present if serial transceiver is used. This is recovered clock by transceiver from the input serial data. for 1G data rate this frequency is 62.5 MHz. For 2.5G rate this is 156.25 MHz.

rxuserclk/

rxuserclk2

Present if serial transceiver is used. This is the looped back version of rxoutclk after passing through a BUFG. When the fabric elastic buffer is not used (1000BASE-X or 2500BASE-X and 100_1000 SGMII modes) this is not used within the core. The BUFG can be replaced in clocking logic with a BUFR-BUFMR/BUFH. For 7 series devices, when RxGmiiClkSrc=RXOUTCLK, rxuserclk2 is twice the RXOUTCLK rate.
gtx_clk Present in TBI Mode 125 MHz
pma_tx_clk Present in TBI Mode 125 MHz
pma_rx_clk Present in TBI Mode 125 MHz
clk625 Present in LVDS Mode 625 MHz
clk208 Present in LVDS Mode 208 MHz
clk104 Present in LVDS Mode 104 MHz

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

This section is not applicable for this IP core.

Transceiver Placement

This section is not applicable for this IP core.