The example designs provided with the core are described in detail in this chapter. For information about the Demonstration Test Bench, see Test Bench.
For all the example designs described in this chapter the file locations for the top level and block level VHDL and Verilog example designs are as follows. The contents of the files, which are different, depending on the core configuration, are described in the respective sections.
The following files describe the top level for the core:
<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/example_design/<component_name>_example_design.v[hd]
The following files describe the block level example design for the core:
<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/example_design/<component_name>.v[hd]