Gearbox_4_to_10_ser8 - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

Converts 4-bit data clocked at 312.5 MHz from ISERDES to 10-bit parallel data clocked at 125 MHz. This data is then presented to the 10b/8b decoder.

The following file describes the gearbox 4 to 10 bit logic:

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/synth/sgmii_lvds_transceiver/<component_name>_gearbox_4_to_10.v