The core has been tested on many hardware test platforms at AMD to represent different parameterizations, including the following:
- The core, used with a device-specific transceiver and using the 1000BASE-X standard, has been tested with the AMD Tri-Mode Ethernet MAC core, which follows the architecture shown in Ethernet 1000BASE-X or 2500BASE-X. A test platform was built around these cores, including a backend FIFO capable of performing a simple ping function, and a test pattern generator. Software running on the embedded Arm® processor provided access to all configuration and status registers. Version 3.0 of this core was taken to the University of New Hampshire Interoperability Lab (UNH IOL) where conformance and interoperability testing was performed.
- The core, used with a device-specific transceiver and using the SGMII standard, has been tested with the AMD LogiCORE™ IP Tri-Mode Ethernet MAC core. This was connected to an external PHY capable of performing 10BASE-T, 100BASE-T, and 1000BASE-T, and the system was tested at all three speeds. This follows the architecture shown in GMII to SGMII Bridge and also includes the Arm based processor test platform described previously.