|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
Adaptive SoC,
AMD UltraScale+™
, AMD UltraScale™
, Zynq UltraScale+ MPSoC,Zynq 7000 SoC, 7 series FPGAs |
| Supported User Interfaces |
GMII
2
|
| Resources |
Performance and Resource Utilization
|
| Provided with
Core
|
| Design Files |
Encrypted RTL |
| Example Design |
Verilog and VHDL |
| Test Bench |
Demonstration Test Bench |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Verilog and VHDL |
| Supported S/W Driver
|
See AXI Ethernet (TEMAC + 1000BASE-X/SGMII) for 1G driver
support |
| Tested Design
Flows
3
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 54667
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support Web
Page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog. For supported family
configurations see Resource Utilization. For supported speed grades
see Speed Grades.
- MII is supported only when used with
EMAC0/EMAC1 present in the Zynq 7000 SoC and
Zynq UltraScale+ MPSoC processing
subsystem (PS).
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|