The steps provided are a useful guide, but additional knowledge is assumed. To help with the guidelines in this mode, see the UltraScale Architecture SelectIO Resources User Guide (UG571). A working knowledge of theAMD Vivado Design Suite is also useful to locate particular clock buffers and slices.
Use the following guidelines:
- All the transmitter and receiver lanes should be within the same BYTE_GROUP.
- All transmitter lanes should be within one nibble and receiver lanes should be within another nibble within the same byte group.
- Nibble selection and placement selection for lanes of the transmitter and receiver must match the Vivado IDE selection of placement constraints.
- The following I/O constraints related to EQUALIZATION, DQS_BIAS, DIFF_TERM, PRE_EMPHASIS must be set appropriately for your application:
Receiver Pins
#IO standard has to be LVDS
set_property IOSTANDARD LVDS [get_ports rxn]
set_property IOSTANDARD LVDS [get_ports rxp]
# Equalization can be set to EQ_LEVEL0-4 based on the loss in the channel.
EQ_NONE is #an invalid option
set_property EQUALIZATION EQ_LEVEL0 [get_ports rxn]
set_property EQUALIZATION EQ_LEVEL0 [get_ports rxp]
#DQS_BIAS is to be set to TRUE if internal DC biasing is used - this is
recommended. #If the signal is biased externally on the board, should be set to
FALSE
set_property DQS_BIAS TRUE [get_ports rxn]
set_property DQS_BIAS TRUE [get_ports rxp]
# DIFF_TERM is to be set to TERM_100 if internal Diff term is used - this is
#recommended. If differential termination is external on the board, should be set to
#TERM_NONE
set_property DIFF_TERM_ADV TERM_100 [get_ports rxn]
set_property DIFF_TERM_ADV TERM_100 [get_ports rxp]
Transmit Pins
#LVDS_PRE_EMPHASIS can be set to TRUE/FALSE based on loss in the line if
pre-emphasis #is desired or not. Note, if PRE -emphasis is desired,
ENABLE_PRE_EMPHASIS attribute #in TXBITSLICE needs to be set to TRUE as
well.
set_property LVDS_PRE_EMPHASIS FALSE [get_ports txn]
set_property LVDS_PRE_EMPHASIS FALSE [get_ports txp]
#IO standard has to be LVDS
set_property IOSTANDARD LVDS [get_ports txn]
set_property IOSTANDARD LVDS [get_ports txp]