MDIO Management Interface Ports - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English
The following table describes the optional MDIO interface signals of the core that are used to access the PCS management registers. These signals are typically connected to the MDIO port of a MAC device, either off-chip or to an internal MAC core. For more information, see Management Registers.
Table 1. Optional MDIO Interface Signal Pinout
Signal Direction Clock Domain Description
mdc Input N/A Management clock (<= 2.5 MHz).
mdio_i 1 Input mdc Input data signal for communication with MDIO controller (for example, an Ethernet MAC). Tie High if unused.
mdio_o 1 Output mdc Output data signal for communication with MDIO controller (for example, an Ethernet MAC).
mdio_t 1 Output mdc 3-state control for MDIO signals; A value of 0 indicates that the value on mdio_out should be asserted onto the MDIO interface.
phyad[4:0] Input N/A Physical Address of the PCS management register set.
  1. These signals can be connected to a 3-state buffer to create a bidirectional MDIO signal suitable for connection to an external MDIO controller (for example, an Ethernet MAC).