Parameters Added from v15.2 to v16.0 - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

The following table lists the parameters added to the core from v15.2 to v16.0.

Table 1. Parameters Added in V16.0
Generic Name Applicability Description Values
NumOfLanes Applicable in asynchronous 1000BASE-X/SGMII mode only Number of lanes of PCS/PMA to be generated 1,2,3
Tx_In_Upper_Nibble Applicable in asynchronous 1000BASE-X/SGMII mode only See Lane Placement Parametersfor details
TxLane0_Placement
RxLane0_Placement
TxLane1_Placement
RxLane1_Placement
EnableAsyncSGMII Selection between synchronous SGMII solution based on component mode vs asynchronous LVDS SGMII solution based on Native mode for UltraScale. Synchronous SGMII can be implemented using Asynchronous Solution. However Synchronous SGMII solution is given in order to maintain backward compatibility.

TRUE: Use Native mode asynchronous solution for SGMII over LVDS implementation.

FALSE: Use Component mode synchronous solution for SGMII over LVDS implementation.

GT_Location Applicable in UltraScale and UltraScale+ device families Selection logic for GT location in terms of X and Y co-ordinates.