Physical Interface - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

Depending on the target architecture, up to three physical interface options are available for the core.

Device Specific Transceiver
Uses a transceiver specific to the selected family to extend the 1000BASE-X functionality to include both PCS and PMA sub-layers. It is available for AMD Versal™ Adaptive SoCs, AMD UltraScale+™ /AMD UltraScale™ , Zynq 7000, AMD Virtex™ 7, Kintex 7 and AMD Artix™ 7 devices. For additional information, see 1000BASE-X or 2500BASE-X with Transceivers.
Ten Bit Interface (TBI)
Provides 1000BASE-X, 2500BASE-X, SGMII or 2.5G SGMII functionality with a parallel TBI used to interface to an external Serializer/Deserializer (SerDes). This is available for Kintex 7 devices.
LVDS Serial
AMD Virtex™ 7 and Kintex 7 devices, -2 speed grade or faster for devices with HR Banks and -1 speed grade or faster for devices with HP Banks for performing the SGMII Standard. AMD Artix™ 7 and Spartan 7 devices, -2 speed grade or higher, can fully support SGMII using standard LVDS SelectIO™ technology logic resources for AMD UltraScale™ /AMD UltraScale+™ devices. Zynq 7000 devices, -2 speed grade or faster for XC7Z010/20 devices and -1 speed grade or faster for XC7Z030/45/100 devices, can fully support SGMII using standard LVDS SelectIO™ technology logic resources. For AMD Versal™ devices, the Advanced IO Wizard is used as a subcore to support the Async LVDS solution. For more information on supported AMD Versal™ devices, refer to Asynchronous SGMII/1000BASE-X Over LVDS. This enables direct connection to external PHY devices without the use of an FPGA transceiver.