Port Changes from v14.3 to v15.0 - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID: PG047
Release Date: 2023-11-01
Version: 16.2 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
Applications
Ethernet 1000BASE-X or 2500BASE-X
1G or 2.5G SGMII
GMII to SGMII Bridge
SGMII to GMII Bridge
1G/2.5G Ethernet PCS/PMA or SGMII Using a Device-Specific Transceiver
GMII Block
PCS Transmit Engine
PCS Receive Engine and Synchronization
Optional Auto-Negotiation Block
Optional PCS Management Registers
Transceiver
Synchronous SGMII over LVDS Using Component Mode
1G SGMII Only
Supported Devices
Asynchronous SGMII/1000BASE-X Over LVDS
Supported Devices
SGMII Using Asynchronous Oversampling over 7 Series FPGAs
SGMII Only
Receiver UI Specification
1G Ethernet PCS/PMA or SGMII with Ten-Bit Interface
8B/10B Encoder
8B/10B Decoder
Receive Elastic Buffer
TBI Block
Recommended Design Experience
Licensing and Ordering
License Checkers
Product Specification
MAC
GMII and 1G or 2.5G SGMII
Physical Coding Sublayer
Ten Bit Interface
Physical Medium Attachment
Physical Medium Dependent
Standards
Performance
Maximum Frequencies
Latency
Latency for 1000BASE-X PCS with TBI
Transmit Path Latency
Receive Path Latency
Latency for 1000BASE-X or 2500BASE-X PCS/PMA Using a Transceiver
Transmit Path Latency
Receive Path Latency
Latency for SGMII
Throughput
Voltage Requirements
Speed Grades
Resource Utilization
BUFG Usage
Port Descriptions
GMII Ports
MDIO Management Interface Ports
Reset Ports
Dynamic Switching Signal Port
DRP and 1588 Support Ports
Configuration and Status Vector Ports
TBI Ports
Transceiver Ports
SGMII Ports
Synchronous SGMII over LVDS Transceiver Interface Ports
Asynchronous SGMII over LVDS Transceiver Interface Ports
RIU Interface Ports
Transceiver Control and Status Debug Ports
Register Space
MDIO Management Interface
MDIO Bus System
MDIO Transactions
Write Transaction
Read Transaction
MDIO Addressing
Physical Address (PHYAD)
Register Address (REGAD)
Connecting the MDIO to an Internally Integrated STA
Connecting the MDIO to an External STA
Management Registers
1000BASE-X or 2500BASE-X Standard Using Optional Auto-Negotiation
Register 0: Control Register
Register 1: Status Register
Link Status
Registers 2 and 3: PHY Identifiers
Register 4: Auto-Negotiation Advertisement
Register 5: Auto-Negotiation Link Partner Base
Register 6: Auto-Negotiation Expansion
Register 7: Auto-Negotiation Next Page Transmit
Register 8: Auto-Negotiation Next Page Receive
Register 15: Extended Status
Register 16: Vendor-Specific Auto-Negotiation Interrupt Control
1000BASE-X or 2500BASE-X Standard without Optional Auto-Negotiation
SGMII Standard Using Optional Auto-Negotiation
Register 4: SGMII Auto-Negotiation Advertisement
Register 5: SGMII Auto-Negotiation Link Partner Ability
SGMII Standard without Optional Auto-Negotiation
Register 15: SGMII Extended Status
Both 1000BASE-X and SGMII Standards
Configuration and Status Vectors
Designing with the Core
General Design Guidelines
Understand the Core Features and Interfaces
Customize and Generate the Core
Examine the Example Design Provided with the Core
Implement the Core in Your Application
Write an HDL Application
Synthesize Your Design and Create a Bitstream
Simulate and Download Your Design
Know the Degree of Difficulty
Keep It Registered
Recognize Timing Critical Signals
Make Only Allowed Modifications
Shared Logic
Clocking
Resets
Reset Structure with Transceiver
Reset Structure with TBI
1000BASE-X or 2500BASE-X with Transceivers
Transceiver Logic for 7 Series and Zynq 7000 Devices
Transceiver Logic For Ultrascale+/UltraScale Devices
Transceiver Logic for Versal Devices
Clock Sharing Across Multiple Cores with Transceivers
Transceiver Files
Transceiver Wrapper
Zynq 7000 and 7 Series Device Transceiver Wizard Files
Support Level
Block Level
SGMII/Dynamic Switching with Transceivers
Receive Elastic Buffer
Selecting the Buffer Implementation from the Vivado Integrated Design Environment
Requirement for the Receive Elastic Buffer
Transceiver Receive Elastic Buffer
Closely Related Clock Sources
Case 1
Closely Related Clock Sources
Case 2
Logic Using the Transceiver Receive Elastic Buffer
Transceiver Logic with the FPGA Logic Receive Elastic Buffer
Transceiver Logic for 7 Series and Zynq 7000 Devices
Transceiver Logic For Ultrascale+/UltraScale Devices
Transceiver Logic for Versal Devices
Clock Sharing Across Multiple Cores with Transceivers and FPGA Logic Elastic Buffer
Transceiver Files
Transceiver Wrapper
Zynq 7000 and 7 Series Device Transceiver Wizard Files
Support Level
Block Level
SGMII Adaptation Module
Synchronous SGMII over LVDS
7 Series and Zynq 7000 Device LVDS
Design Requirements
SGMII Only
SGMII LVDS Clocking Logic
Layout and Placement
LVDS Transceiver for 7 Series and Zynq 7000 Devices
8B/10B Encoder
OSERDES
Gearbox 10b6b
IODELAYs and ISERDES
Eye Monitor and PHY Calibration
Gearbox 6b10b
Comma Alignment
8B/10B Decoder
GPIO SGMII TOP
SGMII PHY IOB
UltraScale Device LVDS
Design Requirements
SGMII Only
Supported Devices
SGMII LVDS Clocking Logic
Layout and Placement
Synchronous SGMII LVDS Transceiver for UltraScale Devices
Delay Controller
Serdes_1_to_10_ser8
Serdes_10_to_1_ser8
Gearbox_10_to_4_ser8
Gearbox_4_to_10_ser8
SGMII Adaptation Module
Support Level
Block Level
Asynchronous 1000BASE-X/SGMII over LVDS
Design Requirements
Asynchronous LVDS Clocking and Reset Logic (Applicable for non Versal devices)
Asynchronous LVDS Clocking and Reset logic (Versal Devices)
Clock Sharing Across Multiple Cores with Asynchronous LVDS Transceiver (Applicable for non Versal devices)
Layout and Placement
Lane Placement Parameters
Layout and Placement in Versal Devices
Asynchronous LVDS Transceiver for UltraScale and Ultrascale+
8B/10B Encoder
tx_ten_to_eight
serdes_1_to_10
Asynchronous LVDS Transceiver for Versal devices
rx_eight_to_ten
The Ten-Bit Interface
Ten-Bit Interface Logic
Transmitter Logic
Receiver Logic
Method 1: Using Only pma_rx_clk0 (Provided by the Example Design)
Method 2: Alternative Using Both pma_rx_clk0 and pma_rx_clk1
Clock Sharing across Multiple Cores with the TBI
Block Level
Using the Client-Side GMII Datapath
Using the Client-Side GMII for the 1000BASE-X Standard
GMII Transmission
Normal Frame Transmission
Error Propagation
GMII Reception
Normal Frame Reception
Normal Frame Reception with Extension Field
Frame Reception with Errors
False Carrier
status_vector[15:0] Signals
Bits[6:2]: Code Group Reception Indicators
Using the Client-Side GMII for the SGMII Standard
GMII Transmission
1/2.5 Gbps Frame Transmission
100 Mbps Frame Transmission
10 Mbps Frame Transmission
GMII Reception
1/2.5 Gbps Frame Reception
100 Mbps Frame Reception
10 Mbps Frame Reception
Additional Client-Side SGMII Logic
SGMII Adaptation Module Top Level
Transmitter Rate Adaptation Module
Interfacing with Client Proprietary Logic/ IP Catalog Tri-Mode Ethernet MAC
Interfacing with Ethernet MAC Peripherals in Device PS
Receiver Rate Adaptation Module
Interfacing with Client Proprietary Logic/IP Catalog Tri-Mode Ethernet MAC
Interfacing with Ethernet MAC Peripherals in Device PS
Clock Generation
Interfacing with Client Proprietary Logic/IP Catalog Tri-Mode Ethernet MAC
Interfacing with Ethernet MAC Peripherals in Device PS
Auto-Negotiation
Overview of Operation
1000BASE-X Standard
SGMII Standard
Using the SGMII MAC Mode to Interface to an External BASE-T PHY with SGMII Interface
Using Both the SGMII MAC Mode and SGMII PHY Mode Configurations to interface to an External BASE-T PHY with a GMII interface
Using the Auto-Negotiation Interrupt
Clock Correction Sequences in Device-Specific Transceivers
Conclusion
Dynamic Switching of 1000BASE-X and SGMII
Typical Application
Operation of the Core
Selecting the Power-On/Reset Standard
Switching the Standard Using MDIO
Auto-Negotiation State Machine
Interfacing to Other Cores
Integration of the TEMAC for 1000BASE-X or 2500BASE-X
Ten-Bit Interface Implementation
Transceiver Implementation
Integration of the TEMAC for Tri-speed SGMII Operation
Ten-Bit Interface Implementation
Transceiver Implementation
Integration of Zynq 7000 Device PS ENET0/1 Using Sync SGMII over LVDS
Integration of the Zynq 7000 Device PS ENET0/1 for 1000BASE-X Operation
Integration of the Zynq 7000 Device PS ENET0/1 for Tri-speed SGMII Operation
Integration of the Zynq 7000 Device PS ENET0/1 Using Device Specific
Integration of the TEMAC Core Using Sync SGMII over LVDS
Special Design Considerations
Power Management
Start-up Sequencing
Loopback
Core with the TBI
Core with Transceiver
Design Flow Steps
Customizing and Generating the Core
Component Name
Board Tab
Ethernet MAC Tab
Select Ethernet
Data Rate Tab
Select Data Rate
Standard Tab
Select Standard
Core Functionality Tab
Physical Interface
Transceiver Options
Advanced IO PLL INPUT Clock
RX Gmii Clk Src
Management Options
SGMII Capabilities Tab
SGMII Operation Mode Tab
Shared Logic Tab
Shared Logic
GT in Example Design
Regeneration of 7 Series/Zynq 7000 Transceiver Files
Output Generation
Examples
Examples Simulation
Synthesis
Simulation
User Parameters
Constraining the Core
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
1000BASE-X or 2500BASE-X with Transceiver Example Design
Transmitter Elastic Buffer
SGMII/Dynamic Switching Using a Transceiver Example Design
Synchronous SGMII over LVDS Example Design (Applicable for Non-Versal Devices)
Top Level
Asynchronous 1000BASE-X/SGMII over LVDS (Applicable for Non-Versal Devices)
Top Level
Asynchronous 1000BaseX/SGMII over LVDS Example Design (Versal Devices)
1000BASE-X with TBI Example Design
Top Level
Transmitter Elastic Buffer
SGMII/Dynamic Switching with TBI Example Design
Top Level
Test Bench
Core with MDIO Interface
Core without MDIO Interface
Customizing the Test Bench
Changing Frame Data
Changing Frame Error Status
Changing the Core Configuration
Changing the Operational Speed
Verification, Compliance, and Interoperability
Simulation
Hardware Testing
Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Ports Added from v15.2 to v16.0
Parameters Added from v15.2 to v16.0
Parameters Removed from v15.2 to v16.0
Ports Added from v15.1 to v15.2
Parameters Added from v15.1 to v15.2
Ports Added from v15.0 to v15.1
Parameters Added from v15.0 to v15.1
Port Changes from v14.3 to v15.0
Ports Added
Ports Removed
Parameters Added
Port Changes from v14.1 to v14.2
Ports Added
Ports Functionality Changed
Port Changes from v14.0 to v14.1
Ports Added
Ports Removed
Port Changes from v13.0 to v14.0
Shared Logic
Ports Removed
Generic Removed
Ports Added
Ports Moved
1000BASE-X State Machines
Introduction
Start of Frame Encoding
The Even Transmission Case
Reception of the Even Case
The Odd Transmission Case
Reception of the Odd Case
Preamble Shrinkage
End of Frame Encoding
The Even Transmission Case
Reception of the Even Case
The Odd Transmission Case
Reception of the Odd Case
Receive Elastic Buffer Specifications
Introduction
Receive Elastic Buffers: Depths and Maximum Frame Sizes
Device Specific Transceiver Receive Elastic Buffers
SGMII FPGA Logic Receive Elastic Buffer
TBI Receive Elastic Buffer
For SGMII / Dynamic Switching
For 1000BASE-X
Clock Correction
Idle Character Removal at 1 Gbps (1000BASE-X and SGMII)
Idle Character Removal at 100 Mbps (SGMII)
Idle Character Removal at 10 Mbps (SGMII)
Maximum Frame Sizes for Sustained Frame
Jumbo Frame Reception
Implementing External GMII
GMII Transmitter Logic (Zynq 7000 and 7 Series)
GMII Receiver Logic
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Solution Centers
Answer Records
Master Answer Record for the 1G/2.5G Ethernet PCS/PMA or SGMII Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Simulation Debug
Hardware Debug
General Checks
Problems with the MDIO
Problems with Data Reception or Transmission
Problems with Auto-Negotiation
Problems in Obtaining a Link (Auto-Negotiation Disabled)
Problems with a High Bit Error Rate
Symptoms
Debugging
Additional Resources and Legal Notices
Support Resources
Finding Additional Documentation
References
Revision History
Please Read: Important Legal Notices

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