Ports Added - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID

PG047

Release Date

2023-11-01

Version

16.2 English

The ports in the following table were added to the core (non-shared logic).

Table 1. Ports Added (non-shared Logic)
Port Name and Width	In/Out	Description	What to do
rxoutclk	Output	`rxoutclk` from the transceiver	This was previously connected internally to clocking elements and routed to `rxuserclk` and `rxuserclk2`. This can be left open if `rxoutclk` can be shared across instances or if not should drive clocking elements.
rxuserclk	Input	Signal from the shared logic block to the transceiver	If `rxoutclk` can be shared across instances, connect O/P of shared logic block. If not, connect to rxoutclk after passing through additional clocking elements.
rxuserclk2	Input	Signal from the shared logic block to the transceiver	If `rxoutclk` can be shared across instances, connect O/P of shared logic block. If not, connect to rxoutclk after passing through additional clocking elements.
gt0_pll0outclk_in	Input	Valid only for AMD Artix™ 7 families. Indicates out clock from PLL0 of GT Common.	Should be connected to signal of same name from GT Common.
gt0_pll0outrefclk_in	Input	Valid only for AMD Artix™ 7 families. Indicates reference out clock from PLL0 of GT Common.	Should be connected to signal of same name from GT Common.
gt0_pll1outclk_in	Input	Valid only for AMD Artix™ 7 families. Indicates out clock from PLL1 of GT Common.	Should be connected to signal of same name from GT Common.
gt0_pll1outrefclk_in	Input	Valid only for AMD Artix™ 7 families. Indicates reference out clock from PLL1 of GT Common.	Should be connected to signal of same name from GT Common
gt0_pll0lock_in	Input	Valid only for AMD Artix™ 7 families. Indicates out PLL0 of GT Common has locked.	Should be connected to signal of same name from GT Common.
gt0_pll0refclklost_in	Input	Valid only forAMD Artix™ 7 families. Indicates out reference clock for PLL0 of GT Common is lost.	Should be connected to signal of same name from GT Common.
gt0_pll0reset_out	Output	Valid only for AMD Artix™ 7 families. Reset for PLL of GT Common from reset FSM in GT Wizard	Should be connected to signal of same name from GT Common or can be left open if not needed.
gt0_qplloutclk_in	Input	Valid only for non AMD Artix™ 7 families. Indicates out clock from PLL of GT Common.	Should be connected to signal of same name from GT Common.
gt0_qplloutrefclk_in	Input	Valid only for non AMD Artix™ 7 Families. Indicates reference out clock from PLL of GT Common.	Should be connected to signal of same name from GT Common.

The ports in the following table were added to the core, but only if the transceiver debug feature was requested during core customization. See the relevant transceiver user guide for more information on using these control/status ports.

Table 2. Ports Added for Transceiver Debug Feature
Port Name and Width	In/Out	Description	What to do¹
gt0_rxchariscomma_out[1:0]	Output	RX character is comma indication	LSB is valid in all cases other than 1588 mode where both the bits are valid.
gt0_rxcharisk_out[1:0]	Output	RX character is K indication	LSB is valid in all cases other than 1588 mode where both the bits are valid.
gt0_rxbyteisaligned_out	Output	RX byte is aligned indication
gt0_rxbyterealign_out	Output	RX byte is realigned indication
gt0_rxcommadet_out	Output	RX comma is detected indication
gt0_txpolarity	Input	Switch the sense of the TXN/P pins
gt0_txdiffctrl[3:0]	Input	Can be used to tune the transceiver TX waveform
gt0_txprecursor[4:0]	Input	Can be used to tune the transceiver TX waveform
gt0_txpostcursor[4:0]	Input	Can be used to tune the transceiver TX waveform
gt0_rxpolarity	Input	Switch the sense of the RXN/P pins
gt0_txprbssel_in[2:0]	Input	TX Pattern Generator control signals to test signal integrity
gt0_txprbsforceerr_in	Input	TX Pattern Generator control signals to test signal integrity
gt0_rxprbscntreset_in	Input	RX Pattern Checker reset
gt0_rxprbserr_out	Output	RX Pattern Checker error output
gt0_rxprbssel_in	Input	RX Pattern Checker control signals to test signal integrity
gt0_loopback_in[2:0]	Input	Loopback within transceiver Note: Loopback is not supported by the core when RxGmiiClkSrc=RXOUTCLK.
gt0_txresetdone_out	Output	Transmitter reset done
gt0_rxresetdone_out	Output	Receiver reset done
gt0_rxdisperr_out[1:0]	Output	Indicates there is disparity error in received data	LSB is valid in all cases other than 1588 mode where both the bits are valid.
gt0_rxnotintable_out[1:0]	Output	Indicates received 10 bit pattern was not found in 8B/10B decode table	LSB is valid in all cases other than 1588 mode where both the bits are valid.
gt0_eyescanreset	Input	Reset the eye scan logic
gt0_eyescantrigger	Input	Trigger the eye scan logic
gt0_eyescandataerror	Output	Signals an error during eye scan
gt0_rxcdrhold	Input	Freeze the CDR loop
gt0_rxlpmhfhold_in	Input	GTP transceiver low-power mode signal
gt0_rxlpmlfhold_in	Input	GTP transceiver low-power mode signal
gt0_rxmonitorout_out[6:0]	Output	GTX/GTH transceiver RX DFE signal
gt0_rxmonitorsel_in[1:0]	Input	GTX/GTH transceiver RX DFE signal
Drive this signal according to the relevant transceiver user guide. If the DRP interface was unused in previous revisions, then generate the core without the Transceiver Debug feature.