Ports Added from v15.0 to v15.1 - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID: PG047
Release Date: 2023-11-01
Version: 16.2 English

The following table lists the ports added from v15.0 of the core to v15.1.

Table 1. Port Changes in v15.1
In/Out	Port Name and Width	Description	What to do
Input	gt_gtrefclk1	Reference clock option for AMD UltraScale+™ /AMD UltraScale™ GT. This is enabled only when debug ports are enabled.
Input	gt_cpllrefclksel[2:0]	Reference clock select line for UltraScale+/UltraScale GT. This is enabled only when debug ports are enabled.	Default value is 3'b001 for gtrefclk0
Input	refclk625_p	LVDS reference clock when LvdsRefclk is selected as 625 MHz.¹
Input	refclk625_n	LVDS reference clock when LvdsRefclk is selected as 625 MHz.¹
Input	refclk156_25_p	LVDS reference clock when LvdsRefclk is selected as 156.25 MHz.¹
Input	refclk156_25_n	LVDS reference clock when LvdsRefclk is selected as 156.25 MHz.¹
Applicable only for UltraScale devices.