The following table does not list the ports separately for multi-lane asynchronous
SGMII/BASE-X over LVDS prefixed with _[lane_number] . The
definition of such signals is the same as the older signal definition except for the
prefixed lane number in the signal name.
| In/Out | Port Name | Description | What to do |
|---|---|---|---|
| In | phyaddr[4:0] | PHY address for the core | This has been converted from a parameter in earlier releases to a port. |
| In | dummy_port_in | Applicable only for Asynchronous 1000BASE-X/SGMII over LVDS mode. Enabled based on placement options for the IP. | Bring this signal to the top level and LOC this port to BITLISCE0 location of the RX_NIBBLE. |
| Out | tx_dly_rdy | Delay ready indication from TX IO logic | For multiple core instantiations connect this output from the instance without shared logic to the tx_dly_rdy_n/rx_dly_rdy_n port of the shared logic in the core. |
| Out | rx_dly_rdy | Delay ready indication from RX IO logic | |
| Out | tx_vtc_rdy | VTC ready indication from TX IO logic | For multiple core instantiations connect this output from the instance without shared logic to the tx_vtc_rdy_n/rx_vtc_rdy_n port of the shared logic in the core. |
| Out | rx_vtc_rdy | VTC ready indication from RX IO logic | |
| Out | tx_logic_reset 1 | Reset for TX fabric logic | Can be kept open for the Ethernet application because enabling of the downstream logic can be handled by the core sync_status. |
| Out | rx_logic_reset 1 | Reset for RX fabric logic | |
| Out | rx_locked 1 | RX PLL locked indication | Can be kept open. |
| Out | tx_locked 1 | TX PLL locked indication | Can be kept open. |
| Out | tx_pll_clkout_phy_en | Port no longer available. | |
| Out | rx_pll_clkout_phy_en | Port no longer available. | |
| Out | tx_bsc_rst_out 1 | TX BITSLICE control reset | For multiple core instantiations connect to the appropriate port in the instance without shared logic in the core. |
| Out | rx_bsc_rst_out 1 | RX BITSLICE control reset | |
| Out | rx_rst_dly_out 1 | Reset to RX delay lines | |
| Out | tx_rst_dly_out 1 | Reset to TX delay lines | |
| Out | tx_bsc_en_vtc_out 1 | Enable VTC indication to TX BITSLICE control | |
| Out | rx_bsc_en_vtc_out 1 | Enable VTC indication to RX BITSLICE control | |
| Out | tx_bs_en_vtc_out 1 | Enable VTC indication to TX BITSLICE | |
| Out | rx_bs_en_vtc_out 1 | Enable VTC indication to RX BITSLICE | |
| Out | riu_clk_out 1 | RIU clock from PLL | Can be kept open. For multiple core instantiations connect to the appropriate port in the instance without shared logic in the core. |
| Out | riu_addr_out[5:0] 1 | RIU address | For multiple core instantiations connect to the appropriate port in the instance without shared logic in the core. |
| Out | riu_wr_data_out[15:0] 1 | RIU write data | |
| Out | riu_wr_en_out 1 | RIU write enable | |
| Out | riu_nibble_sel_out[1:0] 1 | RIU Nibble select | |
| In | riu_rddata_n[15:0] 1 where N=1,2,3 | RIU read data from other BYTE_GROUPS of the bank | |
| In | riu_valid_n 1 Where N=1,2,3 | RIU valid from other BYTE_GROUPS of the bank | |
| In | riu_prsnt_n 1 Where N =1,2,3 | RIU present indication from other BYTE_GROUPS of the bank | |
| Out | rx_btval_n[8:0] 1 Where n=1,2,3 | Calibration output from reset sequence. This is the count value of DELAY corresponding to 800 ps. | |
| Out | clk_rst_debug_out[7:0] | Port no longer available. | |
| Out | tx_pll_clk_out 1 | TX PLL clock to RX IO logic | For multiple core instantiations connect to the appropriate port without shared logic in core. |
| Out | rx_pll_clk_out 1 | RX PLL clock to RX IO logic | |
| Out | tx_rdclk_out 1 | Read clock from TX_BITSLICE FIFO. | |
| In | rx_btval[8:0] 2 | Calibration output from reset sequence. This is the count value of DELAY corresponding to 800 ps. | For multiple core instantiations connect to the appropriate port from the instance with shared logic in the core. |
| In | tx_bsc_rst 2 | TX_BITSLICE_CONTROL reset | |
| In | rx_bsc_rst 2 | RX_BITSLICE_CONTROL reset | |
| In | tx_bs_rst 2 | TX_BITSLICE reset | |
| In | rx_bs_rst 2 | RX_BITSLICE reset | |
| In | tx_rst_dly 2 | Reset to TX delay lines | |
| In | rx_rst_dly 2 | Reset to RX delay lines | |
| In | tx_bsc_en_vtc 2 | Enable VTC to TX BITSLICE control | |
| In | rx_bsc_en_vtc 2 | Enable VTC to RX BITSLICE control | |
| In | tx_bs_en_vtc 2 | Enable VTC to TX BITSLICE | |
| In | rx_bs_en_vtc 2 | Enable VTC to RX BITSLICE | |
| In | riu_clk 2 | RIU clock | |
| In | riu_addr[5:0] 2 | RIU address | |
| In | riu_wr_data[15:0] 2 | RIU write data | |
| In | riu_wr_en 2 | RIU write enable | |
| In | riu_nibble_sel[1:0] 2 | RIU Nibble select | |
| Out | riu_prsnt | RIU present | |
| Out | riu_valid 2 | RIU Valid | |
| Out | riu_rd_data[15:0] 2 | RIU Read data | |
| In | tx_pll_clk 2 | TX PLL clock to IO logic | |
| In | rx_pll_clk 2 | TX PLL clock to IO logic | |
| In | tx_rdclk 2 | Read clock from TX_BITSLICE FIFO. | |
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