Ports Functionality Changed - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID: PG047
Release Date: 2023-11-01
Version: 16.2 English

The functionality of the ports in the following table were changed or corrected as described.

Table 1. Ports Functionality Changed
In/Out	Port Name	Description	What has changed
Output	rxuserclk_out	rxuserclk output	This port is enabled when shared logic is in the core and SGMII/BASE-X modes are selected. It was earlier derived from `txoutclk` in the case of BASE-X mode; now it is the same as `rxoutclk` in the BASE-X and SGMII modes.
Output	rxuserclk2_out	rxuserclk2 output	This port is enabled when shared logic is in the core and SGMII/BASE-X modes are selected. It was earlier derived from `txoutclk` in the case of BASE-X mode; now it is the same as `rxoutclk` in BASE-X and SGMII modes.
Output	resetdone	Reset done indication from the core	Previously this indication was not correct and used to indicate reset done much before completion of the transceiver reset sequence. This has been corrected and indicates the actual reset done of the TX and RX reset sequences.