The ports in the following table were moved under the Transceiver Debug feature of the core (non-shared logic). If these signals were used in the previous version, then the Transceiver Debug feature needs to be enabled and the appropriate signals mapped and remaining signals tied off to default values.
| Port Name and Width | In/Out | Description | What to do |
|---|---|---|---|
| gt0_drpdo_out,gt0_drprdy_out | Outputs | These signals come from the transceiver and should be connected either to an external arbiter or to the signals described in the following row. | If there is no external arbiter, connect these signals directly to the associated signals. If the interface is not used, the signals can be left open. |
|
gt0_drpen_in, gt0_drpwe_in, gt0_drpaddr_in[8:0], gt0_drpdi_in[15:0], gt0_drpclk_in |
Inputs | These signals go to the transceiver, either from an external arbiter or from the signals described in the preceding row. | If there is no external arbiter, connect these signals directly to the associated core signals. If the interface is not used, tie off the signals to ground and gt0_drpclk_in to txusrclk2. |