Register 4: SGMII Auto-Negotiation Advertisement - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

MAC Mode

Figure 1. MDIO Register 4: SGMII Auto-Negotiation Advertisement LOGIC 0's 15 0 Reg 4 1 LOGIC 1 X12856

This register can also be programmed using the optional Auto-Negotiation Configuration interface.

Table 1. Register 4 - SGMII Auto-Negotiation Advertisement
Bits Name Description Attributes Default Value
4.15:0 All bits SGMII defined value sent from the MAC to the PHY RO 0000000000000001

PHY Mode

Figure 2. MDIO Register 4: SGMII Auto-Negotiation Advertisement PHY LINK STATUS ACKNOWLEDGE RESERVED RESERVED 15 14 13 12 11 0 Reg 4 DUPLEX MODE 9 1 10 SPEED RESERVED X12857
Table 2. Register 4: SGMII Auto-Negotiation Advertisement in PHY Mode
Bits Name Description Attributes Default Value
4.15 PHY Link Status

This refers to the link status of the PHY with its link partner across the Medium.

1 = Link Up

0 = Link Down

 R/W 0
4.14 Acknowledge Used by Auto-Negotiation function to indicate reception of a link partner base or Next Page R/W 0
4.13 Reserved Always returns 0, writes ignored Returns 0 0
4.12 Duplex Mode

1= Full Duplex

0 = Half Duplex

 R/W 0
4.11:10 Speed

11 = Reserved

10 = 1 Gbps

01 = 100 Mbps

00 = 10 Mbps

 R/W 00
4.9:1 Reserved Always return 0s Returns 0s 000000000
4:0 Reserved Always returns 1 Returns 1 1