Due to the number of clock domains in this IP core, the reset structure is not simple and involves several separate reset regions, with the number of regions dependent on the core configuration.
The reset from the example design (which is the system reset from the board or any external source) is synchronized with the respective clock domain and then provided to the core, hence it is synchronous reset to the core.
For LVDS Transceiver configuration, the tx_logic_reset and
rx_logic_reset are generated using 156.25MHz clock by a control state
machine. The above two resets are ORed and then synchronized with the core clock to 125 MHz
and provided to the core as reset.
For GT Transceiver configuration, the reset is synchronized with
independent_clock_bufg and provided to the core as reset.