The Vivado Integrated Design Environment (IDE) provides two SGMII capability options for 1G SGMII:
- 10/100/1000 Mbps (clock tolerance compliant with Ethernet specification)
- 10/100/1000 Mbps (restricted tolerance for clocks) or 100/1000 Mbps
For 2.5G SGMII multiple speeds are not applicable.
The first option, 10/100/1000 Mbps (clock tolerance compliant with Ethernet specification) is the default and provides the implementation using the receive elastic buffer in FPGA logic. This alternative receive elastic buffer uses a single block RAM to create a buffer twice as large as the one present in the device-specific transceiver, thus taking extra logic resources. However, this default mode is reliable for all implementations using standard Ethernet frame sizes. Further consideration must be made for jumbo frames.
The second option, 10/100/1000 Mbps (restricted tolerance for clocks) or 100/1000 Mbps, uses the receive elastic buffer present in the device-specific transceivers. This is half the size and can potentially underflow or overflow during SGMII frame reception at 10 Mbps operation. However, there are logical implementations where this can be reliable and has the benefit of lower logic utilization.