This module converts 10-bit parallel data to 1-bit serial data. It instantiates the I/O logic cells (ODELAYE3, OSERDES) and 10-bit to 4-bit gearbox functionality.
The following file describes the serdes 10 to 1 logic:
<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/synth/sgmii_lvds_transceiver/<component_name>_serdes_10_to_1_ser8.v