The LVDS transceiver block fully replaces the functionality otherwise provided by an UltraScale device transceiver. This is only possible at a serial line rate of 1.25 Gbps. The LVDS is split up into several sub-blocks which are described in further detail in the following sections.
The following figure shows a block diagram of the synchronous LVDS transceiver for UltraScale devices. This is split up into several sub-blocks which are described in further detail in the following sections.
On the transmitter path, data sourced by the core netlist is routed through the 8B/10B Encoder to translate the 8-bit code groups into 10-bit data. The 10-bit data is then passed through the 10B4B Gearbox and the 4-bit parallel data is then clocked out serially at a line rate of 1.25 Gbps.
The receiver path has additional complexity. Serial data received at 1.25 Gbps is routed in parallel to two IODELAYE3 and ISERDESE3. The LVDS transceiver block uses the UltraScale device OSERDESE3, IODELAYE3s and ISERDESE3 elements. See the UltraScale Architecture SelectIO Resources User Guide (UG571) for a description of these elements. Logic is provided to find the correct sampling point in the delay controller block.
Then parallel data is fed to the 4B10B gearbox which converts it into 10-bit parallel data. Having recovered parallel data from the serial stream, comma alignment and detection is done on the parallel data. Receiver uses these to realign the 10-bit parallel data to contain unique 8B/10B code groups. These code groups are then routed through the 8B/10B Decoder module to obtain the unencoded 8-bit code groups that the core netlist can accept.
The following files describe the top level of the hierarchal levels of the LVDS transceiver: