Transceiver Control and Status Debug Ports - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English
The following tables show the optional ports that, if enabled, allow the monitoring and control of some transceiver ports. When not selected, these ports are tied to their default values.
Important: The input ports in the Transceiver Control And Status Interface must be driven in accordance with the appropriate GT user guide. Using the input signals listed in the following tables might result in unpredictable behavior of the IP core.
Important: The Dynamic Reconfiguration Port is only available if this option is selected. Driving the DRP interface should be done only after assertion of the gt0_rxresetdone_out signal which indicates the completion of RX reset sequence.
Table 1. Transceiver Control and Status Ports (7 Series and Zynq 7000 Devices)
Signal Direction Clock Domain Description
gt0_drp_addr_in[8:0] Input gt0_drpclk_in DRP address bus
gt0_drpi_in[15:0] Input gt0_drpclk_in Data bus for writing configuration data to the transceiver.
gt0_drpo_out[15:0] Output gt0_drpclk_in Data bus for reading configuration data from the transceiver.
gt0_drprdy_out Output gt0_drpclk_in Indicates operation is complete for write operations and data is valid for read operations.
gt0_drpwe_in Input gt0_drpclk_in DRP write enable
gt0_drpclk_in Input N/A DRP Clock
gt0_rxchariscomma_out[1:0] Output

userclk2 for

non-1588 mode,

rxuserclk2 for

when 1588 enabled.

 GT Status
gt0_rxcharisk_out[1:0] Output

userclk2 for

non-1588 mode,

rxuserclk2 for

when 1588 enabled.
gt0_rxbyteisaligned_out Output rxuserclk2
gt0_rxbyterealign_out Output rxuserclk2
gt0_rxcommadet_out Output rxuserclk2
gt0_txdiffctrl_in[3:0] Input Asynchronous GT TX Driver
gt0_txpostcursor_in[4:0] Input Asynchronous
gt0_txprecursor_in[4:0] Input Asynchronous
gt0_txpolarity_in Input txusrclk2 GT Polarity
gt0_rxpolarity_in Input rxusrclk2
gt0_txprbssel_in[2:0] Input txusrclk2 GT PRBS
gt0_txprbsforceerr_in Input txusrclk2
gt0_rxprbscntreset_in Input rxusrclk2
gt0_rxprbserr_out Output rxusrclk2
gt0_rxprbssel_in[2:0] Input rxusrclk2
gt0_loopback_in[2:0] Input Asynchronous

GT Loopback

Loopback is not supported by the core when RxGmiiClkSrc=RXOUTCLK.
gt0_txresetdone_out Output txusrclk2 GT Status
gt0_rxresetdone_out Output rxusrclk2
gt0_rxdisperr_out[3:0] Output

userclk2 for

non-1588 mode,

rxuserclk2 for

when 1588 enabled.
gt0_rxnotintable_out [1:0] Output

userclk2 for

non-1588 mode,

rxuserclk2 for

when 1588 enabled.
gt0_eyescanreset_in[3:0] Input Asynchronous GT Eye Scan
gt0_eyescandataerror_out Output Asynchronous
gt0_eyescantrigger_in Input rxusrclk2
gt0_rxcdrhold_in Input Asynchronous GT CDR
gt0_rxcdrlock_out Output Asynchronous
gt0_rxlpmen_in Input Asynchronous GT GTX/GTH RX Decision Feedback Equalizer (DFE)
gt0_rxdfelpmreset_in Input Asynchronous
gt0_rxdfeagcovrden_in Input rxusrclk2
gt0_rxmonitorout_out[6:0] Output Asynchronous
gt0_rxmonitorsel_in[1:0] Input Asynchronous
gt0_txpmareset_in Input Asynchronous GT TX-PMA Reset
gt0_txpcsreset_in Input Asynchronous GT TX-PCS Reset
gt0_rxpmareset_in Input Asynchronous GT RX-PMA Reset
gt0_rxpcsreset_in Input Asynchronous GT RX-PCS Reset
gt0_rxbufreset_in Input Asynchronous GT receive elastic buffer Reset
gt0_rxpmaresetdone_out Output Asynchronous GT PMA resetdone indication
gt0_txbufstatus_out[1:0] Output txusrclk2 GT TX Buffer status
gt0_rxbufstatus_out[2:0] Output rxusrclk2 GT RX Buffer status
gt0_dmonitorout_out[16:0] Output Asynchronous GT Status. If width differs for particular family then LSBs valid.
gt0_rxlpmreset_in Input Asynchronous RX LPM reset. Valid only for GTP.
gt0_rxlpmhfoverden_in Input Asynchronous RX LPM-HF override enable. Valid only for GTP.
gt0_txinhibit_in Input txusrclk2 Active-High signal forces TX output to steady state.
Table 2. Transceiver Control and Status Ports (UltraScale Devices)
Signal Direction Clock Domain Description
gt_drp_addr_in[8:0] Input gt_drpclk_in DRP address bus
gt_drpi_in[15:0] Input gt_drpclk_in Data bus for writing configuration data to the transceiver.
gt_drpo_out[15:0] Output gt_drpclk_in Data bus for reading configuration data from the transceiver.
gt_drprdy_out Output gt_drpclk_in Indicates operation is complete for write operations and data is valid for read operations.
gt_drpwe_in Input gt_drpclk_in DRP write enable.
gt_drpclk_in Input N/A DRP Clock. For UltraScale+/UltraScale devices this must be the same value as selected through the Vivado IDE or passed through the DrpClkRate parameter at generation time.
gt_rxcommadet_out Output rxuserclk2
gt_txdiffctrl_in[3:0] Input Asynchronous GT TX Driver
gt_txpostcursor_in[4:0] Input Asynchronous
gt_txprecursor_in[4:0] Input Asynchronous
gt_txpolarity_in Input txusrclk2 GT Polarity
gt_rxpolarity_in Input rxusrclk2
gt_txprbssel_in[2:0] Input txusrclk2 GT PRBS
gt_txprbsforceerr_in Input txusrclk2
gt_rxprbscntreset_in Input rxusrclk2
gt_rxprbserr_out Output rxusrclk2
gt_rxprbssel_in[2:0] Input rxusrclk2
gt_loopback_in[2:0] Input Asynchronous

GT Loopback

Loopback is not supported by the core when RxGmiiClkSrc=RXOUTCLK.
gt_txresetdone_out Output txusrclk2 GT Status
gt_rxresetdone_out Output rxusrclk2
gt_rxdisperr_out[1:0] Output

userclk2 for

non-1588 mode,

rxuserclk2 for when

1588 enabled.
gt_rxnotintable_out[1:0] Output

userclk2 for

non-1588 mode,

rxuserclk2 for when

1588 enabled.
gt_eyescanreset_in[3:0] Input Asynchronous GT Eye Scan
gt_eyescandataerror_out Output Asynchronous
gt_eyescantrigger_in Input rxusrclk2
gt_rxcdrhold_in Input Asynchronous GT CDR
gt_rxcdrlock_out Output Asynchronous
gt_rxlpmen_in Input Asynchronous GT GTX/GTH RX Decision Feedback Equalizer (DFE)
gt_rxdfelpmreset_in Input Asynchronous
gt_txpmareset_in Input Asynchronous GT TX-PMA Reset
gt_txpcsreset_in Input Asynchronous GT TX-PCS Reset
gt_rxpmareset_in Input Asynchronous GT RX-PMA Reset
gt_rxpcsreset_in Input Asynchronous GT RX-PCS Reset
gt_rxbufreset_in Input Asynchronous GT Receive Elastic Buffer Reset
gt_rxpmaresetdone_out Output Asynchronous GT PMA resetdone indication
gt_txbufstatus_out[1:0] Output txusrclk2 GT TX Buffer status
gt_rxbufstatus_out[2:0] Output rxusrclk2 GT RX Buffer status
gt_dmonitorout_out[16:0] Output Asynchronous GT Status
gt_txinhibit Input txusrclk2 Active-High signal forces TX output to steady state.
gt_pcsrsvdin Input Asynchronous See the UltraScale Architecture GTH Transceivers User Guide (UG576) and the AMD UltraScale™ FPGAs Transceivers Wizard LogiCORE IP Product Guide(PG182) for details.
gt_cpllrefclksel[2:0] Input Asynchronous
gt_gtrefclk1 Input N/A