Transceiver Ports - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

The following table shows the transceiver interface ports for the case when Shared Logic is included in the example design and the transceiver is in the core.

Table 1. Transceiver Interface – Transceiver in Core
Signal Direction Description
gtrefclk Input 125 MHz reference clock from IBUFDS to the transceiver for 7 series and Zynq devices. Selectable in GUI for UltraScale+/UltraScale devices.
gtrefclk_bufg Input Reference clock for transceiver which is passed through a BUFG used to drive logic. This is applicable only for 7 series and Zynq devices.
txp Output Transmit differential
txn Output Transmit differential
rxp Input Receive differential
rxn Input Receive differential
txoutclk Output txoutclk from transceiver
userclk Input Also connected to txusrclk of the device-specific transceiver. Clock domain is not applicable.
userclk2 Input Also connected to txusrclk2 of the device-specific transceiver. Clock domain is not applicable.
rxoutclk Output rxoutclk from transceiver
rxuserclk Input Also connected to rxusrclk of the device-specific transceiver. Clock domain is not applicable.
rxuserclk2 Input Also connected to rxusrclk2 of the device-specific transceiver. Clock domain is not applicable.
independent_clock_bufg 1, 2, 3 Input Stable clock in transceiver and also as control clock for IDELAYCTRL. GT Reset controller free running clock in Versal devices.
resetdone Output Indication that reset sequence of the transceiver is complete
pma_reset Input Hard reset synchronized to independent_clock_bufg.
mmcm_locked Input Indication from the MMCM that the outputs are stable.
gmii_txclk Output

Applicable only when GEM is selected as the interface type.

This is the looped back version of userclk2 in BASE-X mode and is the same as sgmii_clk_r in SGMII modes.
gmii_rxclk Output Same as gmii_txclk.
GT COMMON Clock Interface
gt0_pll0outclk_in Input Valid only for Artix 7 families. Indicates out clock from PLL0 of GT Common
gt0_pll0outrefclk_in Input Valid only for Artix 7 families. Indicates reference out clock from PLL0 of GT Common
gt0_pll1outclk_in Input Valid only for Artix 7 families. Indicates out clock from PLL1 of GT Common
gt0_pll1outrefclk_in Input Valid only for Artix 7 families. Indicates reference out clock from PLL1 of GT Common
gt0_pll0lock_in Input Valid only for Artix 7 families. Indicates out PLL0 of GT Common has locked
gt0_pll0refclklost_in Input Valid only for Artix 7 families. Indicates out reference clock for PLL0 of GT Common is lost
gt0_pll0reset_out Output Valid only for Artix 7 families. Reset for PLL of GT Common from reset Finite State Machine (FSM) in GT Wizard
gt0_qplloutclk_in Input Valid only for non Artix 7 families. Indicates out clock from PLL of GT Common
gt0_qplloutrefclk_in Input Valid only for nonArtix 7 families. Indicates reference out clock from PLL of GT Common
  1. For 7 series and Zynq 7000 devices the example design assumes independent_clock_bufg to be 200 MHz. If it is different, the period should be changed in the <component_name>_gtwizard.v[hd] file with the parameter STABLE_CLOCK_PERIOD = 5. This is the period of the stable clock driving this state-machine (in ns). Also, make sure that if the design is using IDELAYCTRL then the value given to this clock is either
    1. within the range of the refclk value specified for IDELAYCTRL or
    2. a different clock is used as the reference clock for IDELAYCRTL.

    Changing the value for STABLE_CLOCK_PERIOD to anything other than 5 might require changing the WAIT_TIMEOUT_2ms counter value in the <component_name>_tx_startup_fsm.v[hd] and <component_name>_rx_startup_fsm.v[hd] files to provide appropriate delays to the FSMs for completion of its startup sequence. The valid range for the stable clock period is 4 to 250 ns. The core has only been tested with 5 ns (that is, 200 MHz).

  2. For UltraScale+/UltraScale devices when the transceiver debug signals are not selected then this is selectable in the Vivado IDE or through the parameter, DrpClkRate. The clock should be free-running and the range for this clock is 6.25–62.5 MHz for the 1 Gbps data rate and 6.25-156.25 for the 2.5 Gbps data rate. When the transceiver debug signals are selected then this can be any frequency depending on the UltraScale+/UltraScale gtwizard recommendation. In this case DrpClkRate corresponds to the Drp Clock port input. Its recommended to keep drp clock and the independent clock to be the same in this case because the core has been tested only for this combination.
  3. For AMD Versal™ devices, the independent clock frequency need not be the same as GT's APB3 clock frequency. Hence, both the clocks can be provided in accordance with their specifications.

The following table describes the interface to the transceiver when Shared Logic is included in the Example design and the transceiver is outside the core.

Table 2. Transceiver Interface – Transceiver Outside Core
Signal Direction Description
gtwiz_userclk_tx_active_out Output Connected to gtwiz_userclk_tx_active_in of GT wizard
gtwiz_reset_clk_freerun_out Output Connected to gtwiz_reset_clk_freerun_in of GT wizard
gtwiz_reset_tx_datapath_out Output Connected to gtwiz_reset_tx_datapath_in of GT wizard
gtwiz_reset_rx_datapath_out Output Connected to gtwiz_reset_rx_datapath_in of GT wizard
gtwiz_reset_all_out Output Connected to gtwiz_reset_all_in of GT wizard
gtwiz_userclk_rx_active_out Output Connected to gtwiz_userclk_rx_active_in of GT wizard
gtwiz_reset_tx_pll_and_datapath_out Output Connected to gtwiz_reset_tx_pll_and_datapath_in of GT wizard
gtwiz_reset_rx_pll_and_datapath_out Output Connected to gtwiz_reset_rx_pll_and_datapath_in of GT wizard
gtwiz_reset_tx_done_in Input Connected to gtwiz_reset_tx_done_out of GT wizard
gtwiz_reset_rx_done_in Input Connected to gtwiz_reset_rx_done_out of GT wizard
gtwiz_buffbypass_rx_reset_out Output Connected to gtwiz_buffbypass_rx_reset_in of GT wizard. Valid when SGMII with fabric elastic buffer or when RX path is on rxuserclk2 or the 1588 solution is selected.
gtwiz_buffbypass_rx_start_user_out Output Connected to gtwiz_buffbypass_rx_start_user_in of GT wizard. Valid when SGMII with fabric elastic buffer or when RX path is on rxuserclk2 or the 1588 solution is selected.
gtwiz_buffbypass_rx_done_in Input Connected to gtwiz_buffbypass_rx_done_out of GT wizard. Valid when SGMII with fabric elastic buffer or when RX path is on rxuserclk2 or the 1588 solution is selected.
gtwiz_buffbypass_tx_reset_out Output Connected to gtwiz_buffbypass_tx_reset_in of GT wizard. Valid only when the 1588 solution is selected
gtwiz_buffbypass_tx_start_user_out Output Connected to gtwiz_buffbypass_tx_start_user_in of GT wizard. Valid only when the 1588 solution is selected
gtwiz_buffbypass_tx_done_in Input Connected to gtwiz_buffbypass_tx_done_out of GT wizard. Valid only when the 1588 solution is selected
rxpmaresetdone_in Input Connected to rxpmaresetdone_out of GT wizard
txresetdone_in Input Connected to txresetdone_out of GT wizard
rxresetdone_in Input Connected to rxresetdone_out of GT wizard
rxmcommaalignen_out Output Connected to rxmcommaalignen_in of GT wizard
rxpcommaalignen_out Output

Connected to rxpcommaalignen_in of GT wizard. For Versal devices, this output is connected to gpi[15:0] input port of GTY/GTYP.

For the bit postion connection refer IP example design or AM002-versal-gty-transceivers user guide.
txelecidle_out Output Connected to txelecidle_in of GT wizard
txpd_out[1:0] Output Connected to txpd_in of GT wizard
rxpd_out[1:0] Output Connected to rxpd_in of GT wizard
rxusrclk_out Output Connected to rxusrclk_in of GT wizard
rxusrclk2_out Output Connected to rxusrclk2_in of GT wizard
txusrclk_out Output Connected to txusrclk_in of GT wizard
txusrclk2_out Output Connected to txusrclk2_in of GT wizard
txctrl0_out[15:0] Output Connected to txctrl0_in of GT wizard
txctrl1_out[15:0] Output Connected to txctrl1_in of GT wizard
txctrl2_out[7:0] Output Connected to txctrl2_in of GT wizard
gtwiz_userdata_tx_out[15:0] Output Connected to gtwiz_userdata_tx_in of GT wizard
rxctrl0_in[15:0] Input Connected to rxctrl0_out of GT wizard
rxctrl1_in[15:0] Input Connected to rxctrl1_out of GT wizard
rxctrl2_in[7:0] Input Connected to rxctrl2_out of GT wizard
rxctrl3_in[7:0] Input Connected to rxctrl3_out of GT wizard
rxclkcorcnt_in[1:0] Input Connected to rxclkcorcnt_out of GT wizard for 1000BASE-X mode or SGMII mode using GT elastic buffer; otherwise 0.
gtwiz_userdata_rx_in[15:0] Input Connected to gtwiz_userdata_rx_out of GT wizard
rxbufstatus_in[2:0] Input Connected to rxbufstatus_out for non-1588 designs and in 1000BASE-X mode or SGMII mode using GT elastic buffer; otherwise 0.
txbufstatus_in[1:0] Input Connected to txbufstatus_out for non-1588 designs; otherwise 0
cplllock_in Input Connected to cplllock_out of GT wizard
rx8b10ben_out Output Connected to rx8b10ben_in of GT wizard
tx8b10ben_out Output Connected to tx8b10ben_in of GT wizard
rxcommadeten_out Output Connected to rxcommadeten_in of GT wizard

The following table describes the interface to the transceiver when Shared Logic is included in the core.

Table 3. Transceiver Interface with Shared Logic in the Core
Signal Direction Description
gtrefclk_p Input 125 MHz differential reference clock to IBUFDS for 7 series and Zynq devices. Selectable in GUI forUltraScale+/UltraScale devices.
gtrefclk_n Input 125 MHz differential reference clock to IBUFDS for 7 series and Zynq devices. Selectable in GUI for UltraScale+/UltraScale devices.
gtrefclk_out Output 125 MHz reference clock from IBUFDS for 7 series and Zynq devices. Selectable in GUI for UltraScale+/UltraScale devices.
gtrefclk_bufg_out Output Reference clock for transceiver which is passed through a BUFG used to drive logic. This is applicable for 7 series and Zynq devices.
txp Output Transmit differential
txn Output Transmit differential
rxp Input Receive differential
rxn Input Receive differential
userclk_out Output Also connected to txusrclk of the device-specific transceiver. Clock domain is not applicable.
userclk2_out Output Also connected to txusrclk2 of the device-specific transceiver. Clock domain is not applicable.
rxuserclk_out Output Also connected to rxusrclk of the device-specific transceiver. Clock domain is not applicable.
rxuserclk2_out Output Also connected to rxusrclk2 of the device-specific transceiver. Clock domain is not applicable.
independent_clock_bufg 1, 2 Input Stable clock in transceiver and also as control clock for IDELAYCTRL.
resetdone Output Indication that reset sequence of the transceiver is complete.
pma_reset_out Output Hard reset synchronized to independent_clock_bufg.
mmcm_locked_out Output Indication from the MMCM that the outputs are stable.
gmii_txclk Output

Applicable only when GEM is selected as the interface type.

This is the looped back version of userclk2 in BASE-X mode and the same as sgmii_clk_r in SGMII modes.
gmii_rxclk Output Same as gmii_txclk.
GT COMMON Clock Interface
gt0_pll0outclk_out Output Valid only for Artix 7 families. Indicates out clock from PLL0 of GT Common.
gt0_pll0outrefclk_out Output Valid only for Artix 7 families. Indicates reference out clock from PLL0 of GT Common.
gt0_pll1outclk_out Output Valid only for Artix 7 families. Indicates out clock from PLL1 of GT Common.
gt0_pll1outrefclk_out Output Valid only for Artix 7 families. Indicates reference out clock from PLL1 of GT Common.
gt0_pll0lock_out Output Valid only for Artix 7 families. Indicates out PLL0 of GT Common has locked.
gt0_pll0refclklost_out Output Valid only for Artix 7 families. Indicates out reference clock for PLL0 of GT Common is lost.
gt0_qplloutclk_out Output Valid only for non Artix 7 families. Indicates out clock from PLL of GT Common.
gt0_qplloutrefclk_out Output Valid only for non Artix 7 families. Indicates reference out clock from PLL of GT Common.
  1. For 7 series and Zynq 7000 the example design assumes independent_clock_bufg to be 200 MHz. If it is different, the period should be changed in the <component_name>_gtwizard.v[hd] file with the parameter STABLE_CLOCK_PERIOD = 5. This is the period of the stable clock driving this state-machine; units are ns. Also, make sure that if the design is using IDELAYCTRL, then the value given to this clock is
    1. either within the range of the refclk value specified for IDELAYCTRL. OR
    2. Some different clock is used as reference clock for IDELAYCRTL.

      Changing the value for STABLE_CLOCK_PERIOD to anything other than 5 might require changing the WAIT_TIMEOUT_2ms counter value in the <component_name>_tx_startup_fsm.v[hd] and <component_name>_rx_startup_fsm.v[hd] files to provide appropriate delays to the FSMs for completion of its startup sequence. The valid range for stable clock period is 4 to 250 ns. The core has only been tested with 5 ns (that is, 200 MHz).

  2. For UltraScale+/UltraScale devices this is selectable through the Vivado IDE or through parameter DrpClkRate. The clock should be free-running and the range for this clock is 6.25-62.5 MHz for 1 Gbps data rate and 6.25-156.25 for 2.5 Gbps data rate.