Clock Resource Sharing across Multiple Cores with RGMII for Tri-Speed Operation - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

Document ID
PG051
Release Date
2023-11-07
Version
9.0 English

Figure 1 illustrates clock resource sharing across multiple instantiations of the core when using RGMII in 7 series devices through HP I/O. Figure 2 illustrates clock resource sharing across multiple instantiations of the core when using RGMII in 7 series devices through HR I/O. For all instantiations, gtx_clk and gtx_clk90 , where present, can be shared between multiple cores, resulting in a common clock domain across the device. The receiver clocks cannot be shared. Each core is provided with its own local version of rgmii_rxc from the connected external PHY device as shown.

In both figures, the upper core instance has been generated with the Shared Logic option enabled. In both cases, this includes an IDELAYCTRL as illustrated. The other core instances have been generated without the Shared Logic option enabled.

The following figures show three cores. However, more can be added using the same principle. This is done by instantiating further cores without the Shared Logic option and sharing gtx_clk across all instantiations. The receiver clock, which cannot be shared, is unique for every instance of the core.

Figure 1. Clock Resource Sharing for Tri-Speed RGMII in 7 Series Using HP I/O
Figure 2. Clock Resource Sharing for Tri-Speed RGMII in 7 Series Devices Using HR I/O