Clocking - 9.0 English

The TEMAC solution has a complicated clocking structure that varies depending upon the specific configuration and the selected FPGA family. The majority of these changes are specific to the physical interface and selected shared logic option. This is described in the following sections:

• Physical Interface for 7 Series and Zynq 7000 Devices
• Physical Interface for UltraScale Devices

The remainder of the clocking for the TEMAC solution is shown in the following figure . These clocks are all dependent on the core configuration:

• s_axi_aclk is present only if the Management type is set to AXI4-Lite.
• mdc is present if the Management type is set to AXI4-Lite and the core is generated with MDIO.
• refclk is only present for GMII or RGMII and if the Shared Logic option “Include shared logic in core” option is selected.
• gtx_clk is not present when physical interface is MII and statistics counters are not enabled.

When the core is generated with the internal interface, it is assumed that it is connected to the Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII core. See the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).