The Ethernet MAC core can be integrated into a single device with the Ethernet 1G/2.5G PCS/PMA or SGMII core to provide either:
- A MAC with an SGMII interface to an external PHY device. SGMII can support either tri-speed (10/100/1000 Mbps) designs or 1 Gbps designs.
- A 1 Gbps or 2.5 Gbps Ethernet MAC core with 1G/2.5G PCS/PMA sublayer functionality: this is a 1 Gbps PHY standard which is most commonly used for a fiber optic medium.
For more details on the AMD Ethernet 1G/2.5G PCS/PMA or SGMII core, see the product web page .
The 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047) provides the information required to connect the two cores together in any supported configuration.
CAUTION:
When using the PCS/PMA-SGMII (transceiver-based)
core for UltraScale family devices, ensure that the signal
resetdone , which is output from the PCS/PMA-SGMII core, is asserted before
using the MDIO interface to access the PCS/PMA-SGMII core.