The following figure illustrates a typical application for a single Ethernet MAC. The PHY side of the core is connected to an off-the-shelf Ethernet PHY device, which performs the BASE-T standard at 1 Gbps, 100 Mbps, and 10 Mbps speeds. The PHY device can be connected using any of the following supported interfaces: GMII/MII, RGMII, or by additionally using the Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII LogiCORE, SGMII.
The user side of the MAC is connected to a processor system through a processor DMA engine. This processor could be running a communications stack, such as the Transmission Control Protocol/Internet Protocol (TCP/IP). For applications such as this, see the AMD Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994). The IP integrator contains an additional IP to connect the user interface of the MAC to the DMA port of a processor. The AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138) describes the AXI Ethernet, which can be instantiated for an intended processor application.
