The example design can be studied as an example of how to do the following:
- Instantiate the core from HDL.
- Source and use the user-side interface ports of the core from application logic.
- Connect the physical-side interface of the core (GMII/MII or RGMII) to device IOBs to create an external interface.
- Derive the required clock logic.
After working with the example design and this product guide, you can write your own HDL application, using single or multiple instances of the core.
Care must be taken to constrain the design correctly, and the constraints provided with the core should be used as the basis for your own purpose. For Vivado Design Suite constraints, see Constraining the Core.
You can simulate the entire design and download the bitstream to the target device.