Configuration of the MAC core is performed using a register bank accessed through the management interface. The configuration registers available in the core are detailed in the following table.
| Address (Hex) | Description |
|---|---|
| 0x400 | Table 2 |
| 0x404 | Table 3 |
| 0x408 | Table 4 |
| 0x40C | Table 5 |
| 0x410 | Table 6 |
| 0x414 | Table 7 |
| 0x418 | Table 8 |
| 0x41C-0x47F | Reserved |
| 0x480 | Priority 0 Quanta Register |
| 0x484 | Priority 1 Quanta Register |
| 0x488 | Priority 2 Quanta Register |
| 0x48c | Priority 3 Quanta Register |
| 0x490 | Priority 4 Quanta Register |
| 0x494 | Priority 5 Quanta Register |
| 0x498 | Priority 6 Quanta Register |
| 0x49c | Priority 7 Quanta Register |
| 0x4a0 | Legacy Pause Refresh Register |
| 0x4A4-0x4F4 | Reserved |
| 0x4F8 | ID Register (0x4F8) |
| 0x4FC | Table 2 |
The contents of each configuration register are shown in the following tables.
| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31:0 | All 1s | R/W 1 |
Pause frame MAC Source Address[31:0]: This address is used by the MAC to match against the destination address of any incoming flow control frames. It is also used by the flow control block as the source address (SA) for any outbound flow control frames. The address is ordered so the first byte transmitted/received is the lowest positioned byte in the register; for example, a MAC address of AA-BB-CC-DD-EE-FF would be stored in Address[47:0] as 0xFFEEDDCCBBAA. |
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| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31 | 0 | R/W | Reset: When this bit is set to 1, the receiver is reset. The bit then automatically reverts to 0. This reset also sets all of the receiver configuration registers to their default values. |
| 30 | 0 | R/W | Jumbo Frame Enable: When this bit is set to 1, the MAC receiver accepts frames over the specified IEEE 802.3-2008 maximum legal length. When this bit is 0, the MAC only accepts frames up to the specified maximum length. |
| 29 | 0 | R/W | In-band FCS Enable: When this bit is 1, the MAC receiver passes the FCS field up to the client as described in User-Supplied FCS Passing. When it is 0, the client is not passed to the FCS. In both cases, the FCS is verified on the frame. |
| 28 | 1 | R/W | Receiver Enable: If set to 1, the receiver block is operational. If set to 0, the block ignores activity on the physical interface RX port. |
| 27 | 0 | R/W | VLAN Enable: When this bit is set to 1, VLAN tagged frames are accepted by the receiver. |
| 26 | 0 | R/W | Half Duplex: If8 set to 1, the receiver operates in half-duplex mode. If 0, the receiver operates in full-duplex mode. |
| 25 | 0 | R/W | Length/Type Error Check Disable: When this bit is set to 1, the core does not perform the length/type field error checks as described in Length/Type Field Error Checks. When this bit is set to 0, the length/type field checks is performed: this is normal operation. |
| 24 | 0 | R/W | Control Frame Length Check Disable: When this bit is set to 1, the core does not mark control frames as bad if they are greater than the minimum frame length. |
| 23:16 | N/A | RO 1 | Reserved |
| 15:0 | All 1s | R/W | Pause frame MAC Source Address[47:32]: See description in the previous table. |
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| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31 | 0 | R/W | Reset: When this bit is set to 1, the transmitter is reset. The bit then automatically reverts to 0. This reset also sets all of the transmitter configuration registers to their default values. |
| 30 | 0 | R/W | Jumbo Frame Enable: When this bit is set to 1, the MAC transmitter sends frames that are greater than the specified IEEE 802.3-2008 maximum legal length. When this bit is 0, the MAC only sends frames up to the specified maximum. |
| 29 | 0 | R/W | In-band FCS Enable: When this bit is 1, the MAC transmitter expects the FCS field to be passed by the client as described in User-Supplied FCS Passing. When this bit is 0, the MAC transmitter appends padding as required, computes the FCS and appends it to the frame. |
| 28 | 1 | R/W | Transmit Enable: When this bit is 1, the transmitter is operational. When it is 0, the transmitter is disabled. |
| 27 | 0 | R/W | VLAN Enable: When this bit is set to 1, the transmitter recognizes the transmission of VLAN tagged frames. |
| 26 | 0 | R/W | Half Duplex: If 1, the transmitter operates in half-duplex mode. |
| 25 | 0 | R/W | Interframe Gap Adjust Enable: If 1, the transmitter reads the value on the port tx_ifg_delay at the start of frame transmission and adjusts the interframe gap following the frame accordingly (see Interframe Gap Adjustment – Full-Duplex Mode Only). If 0, the transmitter outputs a minimum interframe gap of at least twelve clock cycles, as specified in IEEE 802.3-2008. |
| 24:0 | N/A | RO | Reserved |
| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31 | N/A | RO | Reserved |
| 30 | 1 | R/W | Flow Control Enable (TX) : When this bit is 1, asserting the pause_req signal sends a flow control frame out of the transmitter as described in Transmitting a Pause Control Frame. When this bit is 0, asserting the pause_req signal has no effect. This mode should not be enabled at the same time as PFC (Bit[26]). |
| 29 | 1 | R/W | Flow Control Enable (RX) . When this bit is 1, received flow control frames inhibit the transmitter operation as described in Receiving a Pause Frame. When this bit is 0, received flow control frames are always passed up to the client. This mode should not be enabled at the same time as PFC (Bit[25]). |
| 28:27 | N/A | RO | Reserved |
| 26 | 0 | RW | Priority pause flow control enable (TX) . Only present when the core has been generated with PFC support. When this bit is 1, asserting an enabled TX PFC tvalid signal results in a PFC frame being sent from the transmitter. When this bit is 0, the TX PFC tvalid inputs are ignored. This mode should not be enabled at the same time as Flow Control (TX) (Bit[30]). |
| 25 | 0 | RW | Priority pause flow control enable (RX) . Only present when the core has been generated with PFC support. When this bit is 1, received PFC frames assert the relevant enabled RX PFC tvalid outputs as described in Receiving a PFC Frame. When this bit is 0, received PFC frames are ignored and passed to the client. This mode should not be enabled at the same time as Flow Control (RX) (Bit[29]). |
| 24:21 | N/A | RO | Reserved |
| 20 | 1 | RW | TX Auto XON . Only present when the core has been generated with PFC support – this bit defaults to 0 if PFC is not supported. Send a flow control or PFC frame with the relevant quanta set to zero (XON frame) when the relevant, enabled pause request is dropped. |
| 19:16 | N/A | RO | Reserved |
| 15 | 1 | R/W | TX Priority 7 pause enable . Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1, and TX PFC is enabled, assertion or de-assertion of the TX PFC tvalid signal results in a PFC frame being transmitted. When this bit is 0, tx_pfc_p7_tvalid is ignored. |
| 14 | 1 | R/W | TX Priority 6 pause enable . Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1, and TX PFC is enabled, assertion or de-assertion of the TX PFC tvalid signal results in a PFC frame being transmitted. When this bit is 0, tx_pfc_p6_tvalid is ignored. |
| 13 | 1 | R/W | TX Priority 5 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1, and TX PFC is enabled, assertion or de-assertion of the TX PFC tvalid signal results in a PFC frame being transmitted. When this bit is 0, tx_pfc_p5_tvalid is ignored. |
| 12 | 1 | R/W | TX Priority 4 pause enable . Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1, and TX PFC is enabled, assertion or de-assertion of the TX PFC tvalid signal results in a PFC frame being transmitted. When this bit is 0, tx_pfc_p4_tvalid is ignored. |
| 11 | 1 | R/W | TX Priority 3 pause enable . Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1, and TX PFC is enabled, assertion or de-assertion of the TX PFC tvalid signal results in a PFC frame being transmitted. When this bit is 0, tx_pfc_p3_tvalid is ignored. |
| 10 | 1 | R/W | TX Priority 2 pause enable . Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1, and TX PFC is enabled, assertion or de-assertion of the TX PFC tvalid signal results in a PFC frame being transmitted. When this bit is 0, tx_pfc_p2_tvalid is ignored. |
| 9 | 1 | R/W | TX Priority 1 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1, and TX PFC is enabled, assertion or de-assertion of the TX PFC tvalid signal results in a PFC frame being transmitted. When this bit is 0, tx_pfc_p1_tvalid is ignored. |
| 8 | 1 | R/W | TX Priority 0 pause enable . Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1, and TX PFC is enabled, assertion or de-assertion of the TX PFC tvalid signal results in a PFC frame being transmitted. When this bit is 0, tx_pfc_p0_tvalid is ignored. |
| 7 | 1 | R/W | RX Priority 7 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1 and RX PFC is enabled, reception of a PFC frame with a valid quanta for priority 7 is processed as described in Receiving a PFC Frame. When this bit is 0, the rx_pfc_p7_tvalid remains at 0. |
| 6 | 1 | R/W | RX Priority 6 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1 and RX PFC is enabled, reception of a PFC frame with a valid quanta for priority 6 is processed as described in Receiving a PFC Frame. When this bit is 0, the rx_pfc_p6_tvalid remains at 0. |
| 5 | 1 | R/W | RX Priority 5 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1 and RX PFC is enabled, reception of a PFC frame with a valid quanta for priority 5 is processed as described in Receiving a PFC Frame. When this bit is 0, the rx_pfc_p5_tvalid remains at 0. |
| 4 | 1 | R/W | RX Priority 4 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1 and RX PFC is enabled, reception of a PFC frame with a valid quanta for priority 4 is processed as described in Receiving a PFC Frame. When this bit is 0, the rx_pfc_p4_tvalid remains at 0. |
| 3 | 1 | R/W | RX Priority 3 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1 and RX PFC is enabled, reception of a PFC frame with a valid quanta for priority 3 is processed as described in Receiving a PFC Frame. When this bit is 0, the rx_pfc_p3_tvalid remains at 0. |
| 2 | 1 | R/W | RX Priority 2 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1 and RX PFC is enabled, reception of a PFC frame with a valid quanta for priority 2 is processed as described in Receiving a PFC Frame. When this bit is 0, the rx_pfc_p2_tvalid remains at 0. |
| 1 | 1 | R/W | RX Priority 1 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1 and RX PFC is enabled, reception of a PFC frame with a valid quanta for priority 1 is processed as described in Receiving a PFC Frame. When this bit is 0, the rx_pfc_p1_tvalid remains at 0. |
| 0 | 1 | R/W | RX Priority 0 pause enable. Only present when the core has been generated with PFC support- this bit defaults to 0 if PFC is not supported. When this bit is 1 and RX PFC is enabled, reception of a PFC frame with a valid quanta for priority 0 is processed as described in Receiving a PFC Frame. When this bit is 0, the rx_pfc_p0_tvalid remains at 0. |
| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31:30 | 10 | R/W |
MAC Speed Configuration 00 = 10 Mbps 01 = 100 Mbps 10 = 1 Gbps When the TEMAC solution has been generated for 1 Gbps or 2.5 Gbps speed support, bits[31:30] are hard-coded to the value 10. When the TEMAC solution has been generated for 10 Mbps and 100 Mbps speed support, bits[31:30] only accept the values of 00 to configure for 10 Mbps operation, or 01 to configure for 100 Mbps operation. |
| 29:0 | N/A | RO | Reserved |
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| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31:17 | N/A | RO | Reserved |
| 16 | 0 | R/W | RX Max Frame Enable: When Low, the MAC assumes the use of the standard 1518/1522 depending upon the setting of VLAN enable. When High, the MAC allows frames up to RX Max Frame Length irrespective of the value of VLAN enable. If Jumbo Enable is set, this register has no effect. See Maximum Permitted Frame Length. |
| 15 | N/A | RO | Reserved |
| 14:0 | 0x7D0 | R/W | RX Max Frame Length |
| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31:17 | N/A | RO | Reserved |
| 16 | 0 | R/W | TX Max Frame Enable: When Low, the MAC assumes use of the standard 1518/1522 depending upon the setting of VLAN enable . When High, the MAC allows frames up to TX Max Frame Length irrespective of the value of VLAN enable . If Jumbo Enable is set, this register has no effect. See Maximum Permitted Frame Length. |
| 15 | N/A | RO | Reserved |
| 14:0 | 0x7D0 | R/W | TX Max Frame Length |
| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31:16 | 0xFF00 | RW | Pause Quanta refresh value . This register is only present when PFC is enabled at the core customization time. When enabled, this register controls how frequently a PF quanta is refreshed by the transmission of a new PFC frame. When a refresh occurs, all currently active (TX PFC tvalid is High and enabled) priorities are refreshed. |
| 15:0 | 0xFFFF | RW | Pause Quanta value . This register is only present when PFC is enabled at core customization time. When enabled, this register sets the quanta value to be inserted in the PFC frame for this priority. |
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| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31:16 | 0xFF00 | RW | Pause Quanta refresh value . This register is only present when PFC is enabled at the core customization time. When PFC is supported, the 802.3 pause request can also support XON/XOFF Extended Functionality. This controls the frequency of the automatic pause refresh. |
| 15:0 | 0x0 | RO | Reserved |
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