The timing of a normal outbound frame
transfer a 1 Gbps can be seen in Figure 1 with the timing at 100 Mbps shown in Figure 2 and Figure 3. When you want to
transmit a frame, it places the first column of data onto the tx_axis_mac_tdata port and asserts a 1 onto tx_axis_mac_tvalid .
The TEMAC core accepts the first
two bytes of data by asserting tx_axis_mac_tready and then waits until it
is allowed to transmit and it then accepts the remainder of the
frame. You must be capable of supplying new data on the following
cycle when data has been taken, indicated by the assertion of tx_axis_mac_tready . The end of frame is
signaled to the MAC core by asserting tx_axis_mac_tlast on the final byte of the
frame.
At 1 Gbps, data can be taken every 8 ns;
at 100 Mbps, data is taken every 80 ns; at 10 Mbps, data is taken every 800 ns (on an
average). In all the cases, tx_axis_mac_tready qualifies when
data is taken by the MAC. Figure 2 shows the use of tx_axis_mac_tready to
throttle the data when the core has been generated with either an MII or GMII interface. In
this mode, the timing at 100 Mbps and 10 Mbps is identical as tx_mac_aclk is sourced by the PHY at the required frequency (25 MHz or 2.5 MHz).
When the core is generated with an RGMII
interface or the Internal interface the timing at 10/100 Mbps is very different as shown in
Figure 3. In this mode,
the tx_mac_aclk remains at 125 MHz at all MAC speeds and the
tx_axis_mac_tready is activated once every 10 cycles as
shown in Figure 3 or once
every 100 cycles at 10 Mbps. This is not true for the first 2 bytes of frame data where the
data pipeline fills at full rate.
For maximum flexibility in switching applications, the Ethernet frame parameters (destination address, source address, length/type and optionally FCS) are encoded within the same data stream that the frame payload is transferred upon rather than on separate ports.
