Port Additions in v9.0 Rev 4 - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

Document ID
PG051
Release Date
2023-11-07
Version
9.0 English

The following table shows the optional ports added when the Physical Interface is set to Internal and Internal Mode Clock Source is set to RX User Clk2.

Table 1. Added Optional Ports
Port Name and Width Direction Description What to do
rx_usr_clk2 Input Clock for the RX datapath Connect this port to the PCS/PMA core’s rxoutclk port
clk_enable_rx Input Clock enable for the RX datapath Connect this port to the PCS/PMA core’s sgmii_rx_clk_en port