All ports of the Ethernet MAC core level are internal connections in the FPGA logic. An example HDL design provided in both VHDL and Verilog is delivered with each core. The example design connects the core to a FIFO-based loopback example design and adds Input/Output Block (IOB) flip-flops to the external signals of the GMII/MII (or RGMII).
All clock management logic translated from a single onboard clock to the required system clocks are placed in this example design that provides more you more flexibility in implementation (for example, in designs using multiple cores). For information about the example design, See Example Design.
Important: The bus width of the write and read addresses
depends on whether AVB endpoint is enabled or disabled.