Problems with Transmitting and Receiving Frames - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

Document ID
PG051
Release Date
2023-11-07
Version
9.0 English

Problems with data reception or transmission can be caused by a wide range of factors. The following list contains common causes to check for:

  • Verify that the whole TEMAC block is not being held in reset. The whole block is held in reset if the main reset input or if a locked signal from an MMCM is Low.
  • Verify that both the receiver and transmitter are enabled and not being held in reset. For more information, see the receiver and transmitter configuration words in Table 2 and Table 4 respectively.
  • Verify that the TEMAC is configured correctly and that the latest core version is being used. Try running a simulation to check if the failure is hardware-specific.
  • If using GMII or RGMII, check if setup and hold requirements are met For more information, see the section on debugging Implementation and Timing Errors.
  • Verify that the link is up between the PHY and its link partner. If using the Ethernet 1G/2.5G PCS/PMA or SGMII core, see the Debugging Guide section of the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).
  • If using an external PHY, is data received correctly if the PHY is put in loopback? If so, the issue might be on the link between the PHY and its link partner.
  • Check if the address filter is enabled. If frames are not being received correctly, try disabling the address filter to ensure that the frame is not being dropped by the address filter. For more information, see Frame Filter.
  • Verify that the TEMAC has been configured to operate at the correct speed negotiated with the PHY.
  • Are received frames being dropped by user logic because rx_axis_mac_tuser is asserted? See Frame Reception with Errors for details on why frames are marked bad by the Ethernet MAC. The Vivado analyzer tool can be inserted to get more details on the bad frames.
  • Add the Vivado analyzer tool to the design to look at the RX and TX AXI4-Stream and physical interface data signals, control signals, and statistics vectors.