The following table describes the offset control register for the lower 32 bits of seconds field of the RTC, used to force step changes into the counter. When in PTP clock master mode, this can be used to set the initial value following power-up. When in PTP clock slave mode, the software drivers use this register to implement the periodic step corrections.
These register and the register defined in RTC Nanoseconds Field Offset Control are linked. These three offset values are loaded into the RTC counter logic simultaneously following a write to the nanosecond offset register defined in the following table.
| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31:0 | 0 | R/W | 32-bit offset value for the RTC seconds field (Bits[31:0]). Used by the microprocessor to initialize the RTC, then to perform the regular RTC corrections (when in slave mode). |
The following table describes the offset control register for the upper 16 bits of seconds field of the RTC used to force step changes into the counter. When in PTP clock master mode, this can be used to set the initial value following power-up. When in PTP clock slave mode, the software drivers use this register to implement the periodic step corrections.
These register and the registers defined in RTC Nanoseconds Field Offset Control are linked. These three offset values are loaded into the RTC counter logic simultaneously following a write to the nanosecond offset register defined in RTC Nanoseconds Field Offset Control.
| Bits |
Default Value |
Type | Description |
|---|---|---|---|
| 31:16 | 0 | RO | Reserved |
| 15:0 | 0 | R/W | 16-bit offset value for the RTC seconds field (Bits[47:32]). Used by the microprocessor to initialize the RTC, then to perform the regular RTC corrections (when in slave mode). |