Receiver Interface - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

Document ID

PG051

Release Date

2023-11-07

Version

9.0 English

Receive Interface AXI4-Stream Signal Pins describes the receive AXI4-Stream signals used by the core to transfer data to the user. Receive Interface Sideband Signal Pins describes the related sideband interface signals. A detailed description of operation is provided in Receiving Inbound Frames.

Table 1. Receive Interface AXI4-Stream Signal Pins
Signal	Direction	Clock Domain	Description
rx_axis_mac_tdata[7:0]	Out	rx_mac_aclk	Frame data received is supplied on this port.
rx_axis_mac_tvalid	Out	rx_mac_aclk	Control signal for the rx_axis_mac_tdata port. Indicates that the data is valid.
rx_axis_mac_tlast	Out	rx_mac_aclk	Control signal for the rx_axis_mac_tdata port. Indicates the final byte in the frame.
rx_axis_mac_tuser	Out	rx_mac_aclk	Control signal for rx_axis_mac_tdata. Asserted at the end of frame reception to indicate that the frame had an error.
rx_axis_filter_tuser[x:0]	Out	rx_mac_aclk	Per frame filter tuser output. Can be used to send only data passed by a specific frame filter. See Frame Filter for more information.
All signals are active-High.

Table 2. Receive Interface Sideband Signal Pins
Signal	Direction	Clock Domain	Description
rx_statistics_vector[27:0]²	Out	rx_mac_aclk	Provides information about the last frame received.
rx_statistics_valid	Out	rx_mac_aclk	Asserted at the end of frame reception, indicating that the rx_statistics_vector is valid.
All signals are active-High. When PFC is enabled, rx_statistics_vector has a bus width of Bits[28:0].

The following table defines the optional AXI4-Stream AV receive signals included when the AVB functionality is selected.

Table 3. Receive Interface AXI4-Stream AV Signal Pins
Signal	Direction	Clock Domain	Description
rx_axis_av_tdata[7:0]	Out	rx_mac_aclk	Frame data received is supplied on this port.
rx_axis_av_tvalid	Out	rx_mac_aclk	Control signal for the rx_axis_av_tdata port. Indicates that the data is valid.
rx_axis_av_tlast	Out	rx_mac_aclk	Control signal for the rx_axis_av_tdata port. Indicates the final byte in the frame.
rx_axis_av_tuser	Out	rx_mac_aclk	Control signal for rx_axis_av_tdata. Asserted at end of frame reception to indicate that the frame had an error.
All signals are active-High.

The statistics for the frame received are contained within the rx_statistics_vector output. The following table defines the bit field for the vector.

Table 4. Bit Definition for the Receiver Statistics Vector
emacclient rxstats	Name	Description
28	PFC_FRAME	Extra vector bit included when the PFC functionality is included. This indicates that the Ethernet MAC has received a valid PFC frame.
27	ADDRESS_MATCH	If the optional address filter is included in the core, this bit is asserted in case the address of the incoming frame matches one of the stored or pre-set addresses in the address filter. If the address filter is omitted from the core or is configured in promiscuous mode, this line is held High.
26	ALIGNMENT_ERROR	Asserted at speeds less than 1 Gbps if the frame contains an odd number of nibbles and the FCS for the frame is invalid.
25	LENGTH/TYPE Out of Range	If the length/type field contained a length value that did not match the number of MAC client data bytes received and the length/type field checks are enabled, this bit is asserted. This bit is also asserted if the length/type field is less than 46 and the frame is not padded to exactly 64 bytes. This is independent of whether or not the length/type field checks are enabled.
24	BAD_OPCODE	Asserted if the previous frame was error-free and contained the special control frame identifier in the length/type field, but contained an opcode that is unsupported by the MAC (any opcode other than PAUSE).
23	FLOW_CONTROL_FRAME	Asserted if the previous frame was error-free, contained the special control frame identifier in the length/type field, a destination address that matched either the MAC Control multicast address or the configured source address of the MAC, the supported PAUSE opcode, and was acted upon by the MAC.
22	BYTE_VALID	Asserted if a MAC frame byte (destination address to FCS inclusive) is in the process of being received. This is valid on every clock cycle. Do not use this as an enable signal to indicate that data is present on emacclientrxd[7:0].
21	VLAN_FRAME	Asserted if the previous frame contained a VLAN identifier in the length/type field when receiver VLAN operation is enabled.
20	OUT_OF_BOUNDS	Asserted if the previous frame exceeded the maximum frame size as defined in Maximum Permitted Frame Length. This is only asserted if jumbo frames are disabled.
19	CONTROL_FRAME	Asserted if the previous frame contained the special control frame identifier in the length/type field.
18:5	FRAME_LENGTH_COUNT	The length of the previous frame in number of bytes. The count stays at 16368 for any jumbo frames larger than this value.
4	MULTICAST_FRAME	Asserted if the previous frame contained a multicast address in the destination address field.
3	BROADCAST_FRAME	Asserted if the previous frame contained the broadcast address in the destination address field.
2	FCS_ERROR	Asserted if the previous frame received was correctly aligned but had an incorrect FCS value or the MAC detected error codes during frame reception.
1	BAD_FRAME ¹	Asserted if the previous frame received contained errors.
0	GOOD_FRAME¹	Asserted if the previous frame received was error-free.
If the length/type field error checks are disabled, a frame that has an actual data length that does not match the length/type field value is marked as a GOOD_FRAME providing no additional errors were detected. See Length/Type Field Error Checks.