Figure 1. Demonstration Test Bench
The demonstration test bench is defined in the following files:
demo_tb.v[hd]When the MAC data rate is set to 2.5 Gbps, this additional module is present:
loopback_module.v[hd]The demonstration test bench is a simple VHDL or Verilog program to exercise the example design and the core itself. It has two modes of operation, DEMO and Built-in Self Test (BIST), with BIST being the default mode only when the AVB Endpoint is included and frame filter is disabled. When the core is configured for 2.5 Gbps data rate, only the BIST mode of operation is available. In all other configurations, the test bench defaults to DEMO mode.
The test bench consists of the following:
- Clock generators
- DEMO – A stimulus block that connects to the GMII/MII or RGMII receiver interface of the example design.
- DEMO – A monitor block to check data returned through the GMII/MII or RGMII transmitter interface.
- DEMO (Frame Filter enabled) – Basic frame filter that looks at the DA/SA fields of frame inserted into the GMII/MII or RGMII receiver interface.
- BIST – A simple loopback from the GMII/MII or RGMII transmit interface to the receiver.
- BIST (AVB only) – A basic AV data bandwidth monitor.
- BIST (2.5 Gbps only) - A simple pattern checker module for TX and RX. Also, this module loops back the TX data to RX inputs.
- A management block to control the speed selection.
- An MDIO monitor/stimulus to check and respond to MDIO accesses, if a management interface is selected and MDIO is enabled.