The HDL example design supplied with the core for tri-speed (10 Mbps, 100 Mbps, and 1 Gbps) operation provides either a GMII or RGMII interface. These are typically used to connect the MAC to an external PHY device.
The MII defined in IEEE 802.3-2008 specification clause 22, is a parallel interface that connects a 10 Mbps and/or 100 Mbps capable MAC to the physical sublayers. The GMII defined in IEEE 802.3-2008 specification, clause 35, is an extension of the MII and is used to connect a 1 Gbps capable MAC to the physical sublayers. MII can be considered a subset of GMII, and as a result, GMII/MII can carry Ethernet traffic at 10 Mbps, 100 Mbps and 1 Gbps.
The voltage standard used depends on the type of I/O used: HR I/O supports GMII at 3.3 V or lower and HP I/O only supports 1.8 V or lower. Therefore, an external voltage converter is required to interoperate with any multi-standard PHY for GMII.
The RGMII is an alternative to the GMII/MII. RGMII can carry Ethernet traffic at 10 Mbps, 100 Mbps, and 1000 Mbps and achieves a 50% reduction in the pin count compared with GMII. This is achieved with the use of double-data-rate (DDR) flip-flops. RGMII is therefore often favored over GMII by PCB designers. A further advantage of the RGMII implementation is that, unlike GMII/MII, clock resources for the transmitter can be shared across multiple core instances. This results in significant clock resource savings when implementing multiple cores in a design.
The voltage standard used depends on the type of I/O used: HR I/O supports RGMII at 2.5 V or lower and HP I/O only supports 1.8 V or lower. Despite this, being the defined RGMII voltage most PHYs require 2.5 V and therefore an external voltage converter is required to interoperate with any multi-standard PHY for RGMII.