tx_client_fifo_2g5 - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

Document ID
PG051
Release Date
2023-11-07
Version
9.0 English

The tx_client_fifo_2g5 is built around a Dual Port instantiated block RAM, giving a total memory capacity of 4,096 bytes.

When a full frame has been written into the transmit FIFO, the FIFO presents data to the MAC transmitter. The MAC uses tx_axis_mac_tready to throttle the data until it has control of the medium.

If the FIFO memory fills up, the tx_axis_fifo_tready signal is used to halt the AXI4-Stream interface writing in data, until space becomes available in the FIFO. If the FIFO memory fills up, no full frames are available for transmission. For example, if a frame larger than 4,000 bytes is written into the FIFO, the FIFO asserts the tx_overflow signal and continues to accept the rest of the frame from you. The overflow frame is dropped by the FIFO. This ensures that the AXI4-Stream FIFO interface does not lock up.