When this option is selected, the core is generated with an AXI4-Lite memory interface. The core management signals are converted to AXI4-Lite signaling by an instance of the AXI4-Lite IPIF core. See Example Design .
When this option is selected, the core is generated with an AXI4-Lite memory interface. The core management signals are converted to AXI4-Lite signaling by an instance of the AXI4-Lite IPIF core. See Example Design .