When the AXI_IPIF generic is set to TRUE, the CPRI core contains a module to convert between an AXI4-Lite memory mapped interface and the generic memory interface. The module converts between AXI4-Lite and IP Interface (IPIF) signaling. IPIF is mapped to the generic memory interface in the core layer. The core functions as an AXI4-Lite slave. The top level of the AXI interface block is contained in the
axi_lite_ipif_wrapper.vhd
file.
The AXI4-Lite interface signals are described in
Table: AXI4-Lite Memory Mapped Interface
, and the timing is illustrated in
This Figure
and
This Figure
.
Table 3-38:
AXI4-Lite Memory Mapped Interface
|
Port
|
Direction
|
Clock Domain
|
Description
|
|
s_axi_aresetn
|
In
|
Management Clock
|
Global reset source, active-Low
|
|
s_axi_awaddr[11:0]
|
In
|
Management Clock
|
Write address
|
|
s_axi_awvalid
|
In
|
Management Clock
|
Write address valid. This signal indicates that valid write address and control information are available.
|
|
s_axi_awready
|
Out
|
Management Clock
|
Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.
|
|
s_axi_wdata[31:0]
|
In
|
Management Clock
|
Write data.
|
|
s_axi_wvalid
|
In
|
Management Clock
|
Write valid. This signal indicates that valid write data and strobes are available.
|
|
s_axi_wready
|
Out
|
Management Clock
|
Write ready. This signal indicates that the slave can accept the write data.
|
|
s_axi_bresp[1:0]
|
Out
|
Management Clock
|
Write response. This signal indicates the status of the write transaction.
00 - OKAY
10 - SLVERR
|
|
s_axi_bvalid
|
Out
|
Management Clock
|
Write response valid. This signal indicates that a valid write response is available.
|
|
s_axi_bready
|
In
|
Management Clock
|
Response ready. This signal indicates that the master can accept the response information.
|
|
s_axi_araddr[11:0]
|
In
|
Management Clock
|
Read address
|
|
s_axi_arvalid
|
In
|
Management Clock
|
Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledgement signal,
s_axi_arready
, is High.
|
|
s_axi_arready
|
Out
|
Management Clock
|
Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals.
|
|
s_axi_rdata[31:0]
|
Out
|
Management Clock
|
Read data
|
|
s_axi_rresp[1:0]
|
Out
|
Management Clock
|
Read response. This signal indicates the status of the read transfer.
|
|
s_axi_rvalid
|
Out
|
Management Clock
|
Read valid. This signal indicates that the required read data is available and the read transfer can complete.
|
|
s_axi_rready
|
In
|
Management Clock
|
Read ready. This signal indicates that the master can accept the read data and response information.
|
Figure 3-69:
AXI4-Lite Interface Read Timing
|
X-Ref Target - Figure 3-69
|
Figure 3-70:
AXI4-Lite Interface Write Timing
|
X-Ref Target - Figure 3-70
|
