Additional Pipeline Delays - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

The following register-to-register delays must be accounted for in the cable delay calculation.

One datapath clock cycle for the cycle that clocks the transmit data into the transceiver.

In cores supporting line rates above 4,915.2 Mb/s and in all Artix-7 FPGA based cores, one datapath clock cycle to clock the data through the transmit multiplexer. In cores supporting 10,137.6 Mb/s and higher an extra datapath clock cycle is added for the delay through the scrambler.

One recovered clock cycle (Artix-7 devices) or one datapath clock cycle (UltraScale architecture, Zynq-7000 SoC, Virtex-7, and Kintex-7 devices) for the delay from the output of the transceiver into the CDC FIFO. In cores supporting line rates above 4,915.2 Mb/s, there is one extra datapath clock cycle, or recovered clock cycle in Artix-7 devices, to clock the data out of the transceiver.

One datapath clock cycle for clocking the data out of the CDC FIFO.

In cores supporting line rates above 4,915.2 Mb/s, one datapath clock cycle, or recovered clock cycle in Artix-7 devices, for clocking the data through the descrambler.

Two datapath clock cycles for delay in the control path of the R21 coarse timer.

(Artix-7 devices only.) One recovered clock cycle for delay in converting from 2 bytes to 4 bytes.

(12,165.12 and 10,137.6 Mb/s capable cores implemented on Zynq-7000 SoC, Kintex-7, and Virtex-7 devices only.) Two datapath clock cycles to clock the data in and out of the transmit CDC FIFO.

This leads to the additional delays described in the following subsections.