Master CPRI cores have a choice of FIFO depths. In the GUI select either Standard for a depth of 128 words or Extended for a depth of 512 words. Choose Extended when very long transmission lines are to be used, otherwise select Standard.
For example, a CPRI master is running at 10.1 Gb/s line rate, core clock period = 3.255 ns.
Therefore the core can support 64 x 3.255 ns = ±0.21µs of transmission line jitter, where 64 is the mid-point ( fifo_fill_level ) of the CDC FIFO.
The fifo_fill_level can be reduced from 64 to reduce the latency but this also reduces the ability of the CDC FIFO to compensate for transmission line jitter. See Table: FIFO Fill Level Register for details.
In CPRI Master cores, the CDC FIFO is implemented in block RAM.
In 32-bit cores, a RAMB18 is used for Standard CDC FIFO depth and this equates to
4 bytes x 128 = 512 bytes of BRAM, which is 1/4 of the RAMB18. For Extended CDC FIFO depth, this equates to 4 bytes x 512 = 2 KB of block RAM, which is 1 full RAMB18.
In 64-bit cores a RAMB36 is used for Standard CDC FIFO depth and this equates to
8 bytes x 128 = 1 KB of block RAM, which is 1/4 of the RAMB36. For Extended CDC FIFO depth, this equates to 8 bytes x 512 = 4 KB of block RAM, which is 1 full RAMB36.