1. Take the total fixed latency through the transceiver in UI (A).
2. For 8b10b line rates read the barrel shift position through the management interface, this is the transceiver variable latency in UI (B).
For 64b66b line rates using UltraScale architecture-based devices, read the RX and TX gearbox latencies through the management interface. Add them and divide by 8, this gives the transceiver variable latency in UI (B).
For 64b66b line rates using Versal ACAP architecture, read the TX and RX gearbox latencies through the AXI interface of the Versal GT Quad. Add them and divide by 8, this gives the transceiver variable latency in UI (B).
3. Read the RX and if applicable TX CDC FIFO transit times from the management interface. Convert the total transit time to UI (C) as described in Delay Across the CDC FIFO .
4. Add the transceiver total fixed latency (A), the transceiver variable latency (B), the total FIFO transit time (C) and the additional pipeline delay given in the Additional Pipeline Delays section. This sum gives the total delay correction (D).
5. Get the R21 Coarse Timer value from the management interface.
Use the following to convert the R21 coarse timer to UI (E):
° 8b10b line rates : 16-bit datapath cores multiply by 20, 32-bit datapath cores multiply by 40.
° 64b66b line rates : 32-bit datapath cores multiply by 33, 64-bit datapath cores multiply by 66.
6. Add the delay correction (D) to the coarse time value (E) to get T offset in UI.
7. Multiply this by the value shown in Table: Line Speed To UI Conversion Factors to get T offset in ps.