The CPRI core has multiple clock domains:
• The refclk domain. This is the transceiver reference clock at 122.88, 153.6, 245.76, 307.2, 368.64, or 380.16 MHz.
• The auxiliary domain. This is a clock in the range 10 MHz to 125.00 MHz. The management interface runs on this clock as do the blocks programming the DRP ports of the transceiver and the internal PLL used for clock synthesis. This clock must run continuously without interruption as the transceiver and PLL are reconfigured during speed switches.
• The datapath clock domain. In Virtex-7, Kintex-7, Artix-7, and Zynq-7000 SoC devices this is the output from the PLL or MMCM.
• The transceiver clock domain (12,165.12 and 10,137.6 Mb/s cores only). On cores implemented on Kintex-7, Virtex-7, and Zynq-7000 SoC devices, the 316.8 MHz clock is used by the transceiver when running at 10,137.6 Mb/s. This clock runs at 380.16 MHz when operating at 12,165.12 Mb/s. When running at lower speeds, the frequency of the transceiver clock is the same as that of the datapath clock.
• The recovered clock domain. This is the recovered clock from the transceiver, driven from a BUFR or a BUFH.
• The Ethernet clock domain. This is the clock used for the Ethernet C&M channel (if present). If an off-chip GMII interface is used then the transmitter circuitry is in a separate clock domain.
• Hi-speed clock domain. This must be greater than both the maximum transmit and receive clock frequencies and must be unrelated to the reference, datapath or recovered clock.
• GT Wizard Reset Block Free Running clock domain. This must be less than the internal clock frequency of the lowest line rate used.
The following subsections describe how the different clock domains are constrained in the XDC files provided with the example design.