This section describes how to constrain a design that contains the CPRI core. This is illustrated by the constraints files (XDC) that are delivered with the core when it is generated.
Two XDC files are delivered. The <component_name>.xdc file contains the core specific constraints. These include the period requirements for the clocks that are generated in the core support layer and the clock crossing delays between the different core clock domains. The <component_name>_example_design.xdc file contains constraints that are specific to the example design described in Example Design . These include placement constraints for specific devices and constraints on the device input and output signals.
In UltraScale architecture designs the transceiver clock outputs are constrained in an XDC file provided by the UltraScale architecture FPGAs transceivers wizard. This is output in the <component_name>_gt/synth directory.