• UltraScale architecture : The additional delay is 12 datapath clock cycles when operating at 8,110.08, 10,137.6, 12,165.12, or 24,330.24 Mb/s and 10 datapath clock cycles otherwise. 12 datapath clock cycles equates to 396 UI when the core is operating with a 32-bit datapath and 792 UI with a 64-bit datapath. At 8b10b line rates, 10 datapath clock cycles equates to 400 UI when the core is operating with a 32-bit datapath, and 800 UI with a 64-bit datapath.