• UltraScale architecture, Zynq-7000 SoC, Virtex-7, and Kintex-7 devices : The additional delay is eight datapath clock cycles, 160 UI in 16-bit datapath cores and 320 UI in 32-bit datapath cores.
• Artix-7 devices : The additional delay is five datapath clock cycles plus three RECCLK cycles, or 260 UI.